What does this verilog code synthesize to ?

[KaptainBug]

always @ (posedge IN1 or posedge IN2)
  begin
    if IN1
      Y = 0
    elsif IN3
      Y = IN4
    else
      Y = Y
  end

Please ignore any syntax errors.

Few questions

a. Is this a combinational or sequential circuit ?
b. IN3 is not in sensitivity list. So is this asynchronous input ?
c. What are the factors which determine the circuit is sequential other than the clock signal ?

Can you please point me to some websites/lectures for more on synthesis questions.

Thank you.

 

[ads-ee]

disregarding your elsif syntax error in verilog (hint use syntax=verilog tag to show keywords). The posedge IN2 is treated like a clock and posedge IN1 is a async reset. As you are using blocking statements in what is coded as a clocked always block you will likely have a synthesis mismatch.

Qb: IN3 & IN4 aren't in the list as the always block is coded as a synchronous always block. Maybe you should just perform a search on "verilog tutorial"

Qc: using posedge is a good indication.

 

[KaptainBug]

Thank you. This is an interview question. I got your explanation on IN1 and IN2 but not clear on IN3. How is IN3 treated ?

In general, what happens to a signal whenever its inside always statement and not included in sensitivity list ?

 

[mrflibble]

For a couple of useful papers on the subject, google this: sutherland verilog sensitivity list