vreddy
Advanced Member level 4
can anyone elaborate this......
.sdc file:------it contains clk definition to all the paths in deisgn,false & multi cycle path, IO delays, max, min delays, source latency, case analysis........
anthin more files it has/??
wat is this case analysis??
wat is the diff bet timing exceptions & timing constraints??
i think timing exceptions r fals & multi cycle path....correct me if i'm wrong......
thanks in advance
.sdc file:------it contains clk definition to all the paths in deisgn,false & multi cycle path, IO delays, max, min delays, source latency, case analysis........
anthin more files it has/??
wat is this case analysis??
wat is the diff bet timing exceptions & timing constraints??
i think timing exceptions r fals & multi cycle path....correct me if i'm wrong......
thanks in advance