verilog_always
Member level 2
Hi all,
In this protocal if no ACk is sent Master can send STOP bit or Repeated START bit. What does repeated START bit do? Whether it Master has again Start from Scratch that is sending address of slave and so on?
In this protocal if no ACk is sent Master can send STOP bit or Repeated START bit. What does repeated START bit do? Whether it Master has again Start from Scratch that is sending address of slave and so on?