yushionly
Junior Member level 2
hi,i am a newer in verilog,i read this code but do not know the meaning.
what does pipeline #(20) IFIDpipeline mean in verilog? while pipeline is a module i have defined,then what does "#(20) " mean? is it a time delay? Thanks
what does pipeline #(20) IFIDpipeline mean in verilog? while pipeline is a module i have defined,then what does "#(20) " mean? is it a time delay? Thanks