inferring RAM
The HDL synthesis tool recognizes (infers) familiar operations in your HDL code, and translates them into hardware entities such as counters, RAMs, flip-flops, gates, latches, shift-registers, state machines, adders, etc.
Inference is usually a good thing, a big time-saver. However, if you write careless HDL code, the synthesis tool may infer something different than what you intended. It can't read your mind, it only reads what you wrote.
Your synthesis tool users manual should explain how to write HDL code that helps the synthesis tool correctly infer various hardware features such as an FPGA Block RAM. For example, the Xilinx XST User Guide chapter "HDL Coding Techniques".