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A async feedback is a loop, which design compiler will complain upon.
In very simple terms if you short an output of a gate such as an AND gate, OR gate or any other combi logic gate to its input, it will become an async loop.
In more general terms, if you feed back an ouput of a combinational gate(not register or latch) to the input of another combinational gate(not register or latch), without a sequential element(a register) in the path, it becomes a loop which will cause a loop error.
In some cases this loops are desirable for exemple when designing asynchronous circuits, take the exemple of an huffman gate. What happen if i ignore loops, generate netlist and make my ICs ?
Will the ICs be functionnal ?