What does loop error mean when synthetizing with Design Compiler?

[master_picengineer]

Hi,

Can someone explain me what means loop error while synthetizing with design compiler. Who can explain the phenomenon ?

Thanks in advance !

 

[avimit]

Re: loop in Design

A async feedback is a loop, which design compiler will complain upon.
In very simple terms if you short an output of a gate such as an AND gate, OR gate or any other combi logic gate to its input, it will become an async loop.
In more general terms, if you feed back an ouput of a combinational gate(not register or latch) to the input of another combinational gate(not register or latch), without a sequential element(a register) in the path, it becomes a loop which will cause a loop error.
Kr,
Avi
http://www.vlsiip.com

 

[master_picengineer]

loop in Design

Thanks Sir,
In some cases this loops are desirable for exemple when designing asynchronous circuits, take the exemple of an huffman gate. What happen if i ignore loops, generate netlist and make my ICs ?
Will the ICs be functionnal ?

Thanks again !

 

[avimit]

Re: loop in Design

I dont know of any condition where loops may be desireable. And if you make an IC with async loops it will NOT work
Kr,
Avi

 

[master_picengineer]

loop in Design

That's fine, Thanks a lot.
Cheers,
Master_PicEngineer