What are Voltage Levels For LVDS and RS422 signals

[srinivasa]

Hi

What are voltage levels for LVDS and RS422 .Means what is the voltage level for 1 and 0 .for example in TTL(input) logic 1 is represented above 2.4V and 0 it is < 0.8 . and In RS232 1 is -5 to -15 and for 0 it is +5 to +15. i want to interface RADAR(RS422) with FPGA(LVDS). If anyone know answer please reply

Thanks and Regards
srinivasa

 

[ckshivaram]

https://focus.ti.com/lit/an/slla031a/slla031a.pdf


LVDS overcomes some of the limitations of more traditional signaling standards such as RS-422. LVDS cuts down on noise and boosts data rates by using extremely low voltage levels (350 mV compares to 2.4 V), which translates to low radiation and less power consumption. Most important, differential signaling allows the receiver to filter out noise. This is done by sending signals across two wires simultaneously, each with opposing current and voltage swings. The actual data is read as the difference in amplitude between the signals on the two wires. If noise is induced, it will appear on both lines, but the signal information remains unchanged. Since the signal has improved noise immunity, voltage can be reduced and data rate can be increased.

 

[srinivasa]

Hi

What is the exactly the difference voltage levels for 1 and 0.

Thanks
Srinivasa

 

[ckshivaram]

You may not connect RS422 directly to an FPGA. Even if a differential buffer would exist. RS422 inputs need to have a common mode range of +/- 10V.
So before interfacing to your FPGA, use a RS422 differential line receiver.

Please Keep it in mind. you may damage fpga board

---------- Post added at 14:09 ---------- Previous post was at 14:01 ----------

trying to interface camera or using RGB in your project

 

[srinivasa]

Thanks for your reply , First i am converting the RS422 to LVTTL and then LVTLL to LVDS .But i want the exact information on volatge levels , what are the voltage range LVDS and RS422 can accept.

thanks
srinivasa

 

[FvM]

There are official standards defining the voltage levels, but you'll find sufficient detailed specification in any datasheet of a chip dealing with the respective I/O standards, e.g. FPGA or a level converter. I guess, you didn't yet look into it.

 

[allanvv]

Can't you just google it?

 

[ckshivaram]

http://www.fairchildsemi.com/an/AN/AN-5017.pdf

this should resolve all your querries. understand this application note. there can be no other document better than application note by the manufacturer in the entire web.

---------- Post added at 14:59 ---------- Previous post was at 14:57 ----------

**broken link removed**

this should be an icing on the cake for you.

 

[dick_freebird]

TIA-422, TIA-644 specs contain excruciating detail for you
to absorb.

RS-422 is more fault tolerant and a nominal 4V difference.
RS-485 is additionally fault tolerant. LVDS is for a shorter
haul and a more electrically benign environment.

There is not an "exactly" difference voltage, there is a
range of allowed "must produce" at the transmitter and
a "must accept" at the receiver.

RS-422 is something like 2V min output diff and 400mV
max input diff. LVDS, 200-250mV and 50mV if I recall.
You can look it up or refer to manufacturer datasheets
and app notes for 26x31/32 (RS-422) and 90x31/32
(LVDS) families.