What are the various reasons for the 0-1 and 1-0 mismatches while simulations?

[Pinto$]

Hi,
I was doing simulations of some ATPG testbench and i found that while doing verilog simulations for scan parallel, chain serial and scan serial patterns, there were a lot of 0-1 and 1-0 mismatches. can anyone suggest me why could there be so large no. of mismatches and how could i improve my simulations?
Please respond.
Regards,
Pinto$

 

[rca]

1-mismatch between model used by the ATPG tool and the simulation, for example, analog module, memories/pads...
2-timing issues (hold/setup), if you simulated back annotated netlist, you must have this one timing clean, to avoid wrong capture/shift.
3-checks all error during the simulation, that should indicate what goes wrong.

 

[Pinto$]

1-mismatch between model used by the ATPG tool and the simulation, for example, analog module, memories/pads...
2-timing issues (hold/setup), if you simulated back annotated netlist, you must have this one timing clean, to avoid wrong capture/shift.
3-checks all error during the simulation, that should indicate what goes wrong.

Hi rca,
I am doing no timing simulation. but problem is that at one place in the system clock, one clock pulse is sort of missing which i think is doing blunders. Can it be due to test procedure generated by scan insertion tool?
nyways what steps have to be taken if there is a mismatch between models used by atpg tool and simulation tool?

 

[rca]

modify your atpg model to reflect correctly the "reality".
I don't understand your clock issue

 

[airqqy]

Pls check your simulation envioment, u should define simulaition don't check setup/hold timing when use no back annotated netlist.

 

[Pinto$]

When I checked the waveforms for all the scan chain which is showing mismatches, I observed that there are 3 flops in scan chains for which no shifting is taking place. I mean for 3 flops, Q is coming out to be equal to SI (scan input). I have tried changing the models but problem is still not resolved. The important thing to be noted is that the same flop model is being used in other scan chains which are working fine. As I am doing no timing simulations there is no issue of timing delays also. I have also tried to not include the mismatches creating flops in the scan chain but this time flops following the earlier flops are showing mismatches (i.e. Q coming out to be equal to SI). I am stuck with this problem.
Please suggest.
Many thanks.

---------- Post added at 18:16 ---------- Previous post was at 18:08 ----------

modify your atpg model to reflect correctly the "reality".
I don't understand your clock issue

Hi rca,
What do you mean by "reality"?
I am doing simulations for stuck at faults so I just need to give the test patterns generated by ATPG tool to the simulation tool?
Is this good or do I have to give some additional constraints somewhere in between?

Thanks