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Extraction can happen in different modes and different process corners.
From the fab, we get the RC data for different corners (for example slow/fast/nominal etc).
when we talk about modes, extraction can happen for ASIC's during the design process at
1. Global mode (post global routing).
2. Final mode (post detailed routing).
In Global mode, once RC's are extracted, the delay model that is used is elmore.
Elmore is a distributed resistance and lumped capacitance model. It accounts for only one pole and hence fast but can introduce some inaccuracy.
In final mode, the delay model is AWE (asymptotic waveform evaluation). AWE is more accurate because it is a > 2 pole model.
Delay models are important because the delay calculator provides this delay information back to STA (static timing analysis) engine.
Extraction is so important because it effects STA (static timing analysis), which dictates if you met your setup and hold times at every single flop in your chip.
STA actually finds the longest(critical) path in your circuit which determines your circuit frequency and also if you met all your hold times in your circuit.
STA uses extraction data at fast corner while calculating hld and slow data while calculating setup to be pessimistic as possible so that your chip doesn't fail after it comes back from the fab.
Extraction can also be classified as Lumped and coupled. In lumped you basically try to reduce a large RC circuit into an equivalen smaller RC circuit just taking the dominant poles into account (without any coupling). This is important because you want to reduce large RC circuits to smaller one's so that you can save on computer memory and run times.
In coupled mode, you basically try to extract the coupling capacitances which contribute to analyzing your crosstalk delay/noise effects on your chip.
If we are extracting for gate level, we have an equivalent RC circuit representation for each gate, which represents the gate Input/Output capacitances along with holding resistances. We plug these models into the RC network. But this is only for delay computation purpose (especially for fast slew propagation). But this can be inaccurate. Hence we dont represent gates using RC's. Rather we represent them using NLDM's and .libs (liberty format).
Reduction only happens mostly for passive components (wires) and not active elements. This reduction we term as model order reduction (MOR).
We usually plug in .lib (liberty) models for gates. Liberty models have tables which show gate delay as a function of (input transition time/output loads).
what we use at global and final mode for extraction is usually called a 2.5D extractor. This makes use of rules which are generated using a 3D extractor.
A 3D extractor is most accurate as it uses maxwells equations (to be precise green's function) to calculate RC's of various geometries which your fabrication facility will most likely manufacture.