anilineda
Member level 3
Hello all,
Is there any way of increasing the rated speed of the design , otherthan modifying the code.
i thought of physical constriants to constraint routing paths in fpga fabric which will alter the longer paths to smaller ones and hence increases the operating speed . (educate me, if im wrong anywhere)
so,can i do something with timing constraints to UP the operating frequency without violating the paths .? if yes, what are those and give me the reference to know more.
regards,
Anil
Is there any way of increasing the rated speed of the design , otherthan modifying the code.
i thought of physical constriants to constraint routing paths in fpga fabric which will alter the longer paths to smaller ones and hence increases the operating speed . (educate me, if im wrong anywhere)
so,can i do something with timing constraints to UP the operating frequency without violating the paths .? if yes, what are those and give me the reference to know more.
regards,
Anil
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