What are the methods to avoid metastability?

[abhineet22]

To avoid metastability problem v use synchronizers..
does any other method to avoid it?

 

[banjo]

Metastability?

If the metastability problem is because you are crossing between clock domains, you can detect the problem and correct for it. The correction involves switching the downstream capture clock to the opposite clock edge.
Assume that the rising edge of the driving clock domain and the rising edge of the receiving clock domain and closely, but not exactly aligned. Metastability can occur. However, if you switch to using the falling edge clock on the receiving clock domain, then ~ 1/2 period of setup time should be available. If you place tight routing constraints on the flop following the receive capture flop then you can move back to a rising edge capture on the second stage and everything is normal from then on.

All the above assumes that the two clock domains differ in phase, but have the same period. If the two clocks are at different frequencies, then the meta points will move with the passage of time and this technique will not work.

 

[rberek]

Re: Metastability?

When you have two different clocks with no phase or frequency relationship, the only way I can think of to avoid some form of metastability hardening is to ensure by design that a control signal generated in one clock domain won't be sampled by the other clock domain until it is guaranteed to be stable.

1) The signal being sampled is basically DC. For example, a configuration bit from one of your software registers that was set at setup of the device and rarely changes. This bit could be sampled by the receiving clock domain directly. Be careful though, as those pesky software designers might decide to change their mind and flip those register bits more frequently!

2) A defined bus protocol where signals are guaranteed to be stable for a time period before another controlling signal is present. For example, a Motorola style processor bus where the address is guaranteed to be present a clock or two before the Data Strobe. Then you would have to synchronize the Data Strobe but may not have to synchronize all the address bits.

Now, for datapaths, Rate Adapt FIFOs can be used to store data in one clock domain and read it out in the other clock domain. The FIFO's handshaking and other control signals would still have to be metastability hardened, but the wider datapath would not.

In general, I'm not aware of a way to do away with synchronizers altogether in a multiple clock domain scenario (unless it is a scenario like banjo described), but you do not necessarily have to synchronize every signal crossing a clock domain if you are careful.

I apologize if this is old news to you!

r.b.

 

[arnoud]

Re: Metastability?

Metastability is unavoidable if you have multiple async clock domains.

Ways to transfer information between clock domains are:

- multiple flip flops inseries - one signal one direction, slow, simple
- Fifo - wider databusses & higher datarates possible, complex
- smart handshaking - somewhere between above 2 solutions.

 

[funster]

Re: Metastability?

using synchonizer is a only method for metastability.

the other methods are all from simple synchronizer.

Best regards

To avoid metastability problem v use synchronizers..
does any other method to avoid it?

 

[salma ali bakr]

Re: Metastability?

you can make your design globally asynchronous and locally synchronous
that's if it's a SoC for instance