Delaying power supplies by putting RCD networks in the current
path seems like a pretty wasteful way to go. And to get a long
delay at amperes of through-current probably means sub-ohm
resistance and ridiculously-sized delay caps as a result (maybe
the input filter of the POLs is big enough, but I've never put
more than a couple of millifarad on any board).
Gate control of a MOSFET would at least afford you the option
that series R approaches zero, when the sequencing is done.
Op amp control of gate can give you whatever risetime (and,
if a second independent amp and shunt FET replaces the
reverse diode and discharge shunt R, fall time) you want, as
long as it respects the op amp bandwidth / slew rate.
If you look at sequencer / supervisor ICs internal and/or
application schematics, they don't put any series R in the
power path.