Re: from 130nm to 65nm
Process technology: .18um --> .13um --> 90nm --> 65nm
Challenges just like linuxluo mentioned above,
1) Leakage power,
2) SI (crosstalk), and
3) Yield
are physical/implementation related.
RTL coding does not have much to do with them.
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However for MSV(multiple supply voltage) designs,
appropriate hierarchy of Verilog modules may be helpful for implementation tools.
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