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Interconnect Delay: As you shrink the technology the interconnect wires does not reduce because of that more capacitances occurs. Also congestion may become high.
Process technology: .18um --> .13um --> 90nm --> 65nm
Challenges just like linuxluo mentioned above,
1) Leakage power,
2) SI (crosstalk), and
3) Yield
are physical/implementation related.
RTL coding does not have much to do with them.
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However for MSV(multiple supply voltage) designs,
appropriate hierarchy of Verilog modules may be helpful for implementation tools.
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jothi read cdnusers.org
article on 130-to -65nm migration
and also very good discussion on it.
see also CDN conference paper uploaded on eda books upload/download?
as we move to submicro technologies,ir drop is the key issye...bcz of following reasons
1.ir drop act on clock tree by jitter imapct ,which impacts slicing of input data
2.in datapath it impacts by timingfailures
3.and by electromigration it will effect on life of an ic itself.
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