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What are the biggest design challenges when we move from 130 to 90 and 65?

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jothi

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What are the biggest design challenges from PD perspective when we move from 130 to 90 and 65 ?
 

carrot

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Re: from 130nm to 65nm

Hi,

Interconnect Delay: As you shrink the technology the interconnect wires does not reduce because of that more capacitances occurs. Also congestion may become high.

Apart from that crosstalk may also increse.
 

politicante

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Re: from 130nm to 65nm

Hi,

don't forget about leakage problems
 

linuxluo

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Re: from 130nm to 65nm

hi,
signal integrity/power/design for yield/design for manufacture
 

bronzefury

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Re: from 130nm to 65nm

What could an RTL coder do to make transition smoother?
 

joe2moon

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Re: from 130nm to 65nm

Process technology: .18um --> .13um --> 90nm --> 65nm

Challenges just like linuxluo mentioned above,
1) Leakage power,
2) SI (crosstalk), and
3) Yield
are physical/implementation related.

RTL coding does not have much to do with them.
----------------------------------------------------------------------------------

However for MSV(multiple supply voltage) designs,
appropriate hierarchy of Verilog modules may be helpful for implementation tools.
----------------------------------------------------------------------------------
 

gafsos

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Re: from 130nm to 65nm

hi,

if u decrease a mos length u increase a leakage. so from 130nm to 65 nm . some considreation must be in account.

thx
 

aravind

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from 130nm to 65nm

jothi read cdnusers.org
article on 130-to -65nm migration
and also very good discussion on it.
see also CDN conference paper uploaded on eda books upload/download?
 

visualart

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from 130nm to 65nm

In my opinion, the SI is the No1 of the challenges.

in the next place, the drive, OPC, and the clock tree, multivalotage is the challenge too.
Code:
 

pandit_vlsi

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Re: from 130nm to 65nm

as we move to submicro technologies,ir drop is the key issye...bcz of following reasons
1.ir drop act on clock tree by jitter imapct ,which impacts slicing of input data
2.in datapath it impacts by timingfailures
3.and by electromigration it will effect on life of an ic itself.
 

jitendra

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Re: from 130nm to 65nm

Can anyone provide Paper / document for challenges in 90 & 65nm ?

Thanks
 

xuzaiwang

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Re: from 130nm to 65nm

ESD circuit maybe a key point!
and the IR dorp
 

research235

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from 130nm to 65nm

Hello Jitender ,

If u have access to IEEE please chech them, U will get many docs .. Else try searching like LOW POWER DIGITAL DESIGN in google

WELCOME TO LOW POWER !!!

Suresh
 

anishrai

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Re: from 130nm to 65nm

i dont have much idea but hope this pdf helps u....
 

qingliliu

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from 130nm to 65nm

i want to know more too, thanks a lot
 

birdiee470

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from 130nm to 65nm

65 nm tech only suitable for digital design,,, if you implement in analog design u will have trouble in noise and bandwidth,
 

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