Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

Status
Not open for further replies.

panos_papajohn

Member level 2
Joined
Mar 18, 2011
Messages
46
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,640
Hi everyone,

I wrote a VHDL script for interfacing the DAC on the Spartan3E board with the FPGA. When I am running the synthesis tool I get the following warning : WARNING:Xst:1293 - FF/Latch <SPI_signal_0> has a constant value of 0 in block <SPI>. This FF/Latch will be trimmed during the optimization process.

I don't get why since I have gave a value to this signal. I need to fix this cause the simulation doesn't work correctly. This is the code :
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SPI is
  port(clk,  ALOAD : in std_logic;
        D   : in std_logic_vector(11 downto 0);
        SO  : out std_logic;
		  clock_out : OUT STD_LOGIC;
		  chip_select : OUT STD_LOGIC);
end SPI;
architecture archi of SPI is

  signal SPI_signal: std_logic_vector(31 downto 0) := (others => '0'); 
  signal data1 : std_logic_vector (11 downto 0):= (others => '0');
  signal clock : std_logic ;
  
  begin 
 
 process (clk, ALOAD, data1,SPI_signal,D)
 
		variable chip : std_logic;
   begin

-- Shift registers implements the SPI communication
    if (ALOAD='0') then
	
	 --Disable DAC 
	 
		chip :='0'; 
		chip_select <= chip;
		 data1<=D;
	 --Create the data stream for the ADC on the SPARTAN3E board.
	SPI_signal <= "1010"& data1 & "0000" & "0011" & "10101010";
       
	
		elsif (clk'event and clk='1') then
      SPI_signal <= SPI_signal(30 downto 0) & '0';
      SO <= SPI_signal(31);  
		
		--Enable DAC for the data conversion
		
		chip :='1'; 
		chip_select <= chip;
		
    end if;

 end process;
 
 --Clock output for the DAC
 
	clock<=clk;
clock_out <= clock;

end archi;

If anyone could help my I would appreciate it. AS you can tell Im to VHDL so be patient please:grin:
 

j_andr

Full Member level 4
Joined
Mar 30, 2008
Messages
208
Helped
59
Reputation
118
Reaction score
37
Trophy points
1,308
Location
europe
Activity points
2,491
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

I have gave a value to this signal <SPI_signal_0>

look:

SPI_signal <= "1010"& data1 & "0000" & "0011" & "10101010";
/.../
SPI_signal <= SPI_signal(30 downto 0) & '0';

J.A
 

panos_papajohn

Member level 2
Joined
Mar 18, 2011
Messages
46
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,640
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

Yes I know that the problem is in these two lines but I don't understand why. It shouldn't give any warnings.. Do you have assumptions about this?
 

j_andr

Full Member level 4
Joined
Mar 30, 2008
Messages
208
Helped
59
Reputation
118
Reaction score
37
Trophy points
1,308
Location
europe
Activity points
2,491
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

do you have any conditions where LSB of SPI_signal gets other
value then '1' ?
if not - synthesis tool treats it as hardwired to '0' and removes FF;
if it's your intention you can ignore the warning but synthesis can not assume
it so it issues a message 'it might be a problem in the code here';


J.A
 

panos_papajohn

Member level 2
Joined
Mar 18, 2011
Messages
46
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,640
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

Ok I get that. But the values that I concatenated to the SPI_signal must have this value cause there are commands for the DAC. Is there any way to counter this warning?
 

j_andr

Full Member level 4
Joined
Mar 30, 2008
Messages
208
Helped
59
Reputation
118
Reaction score
37
Trophy points
1,308
Location
europe
Activity points
2,491
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

Is there any way to counter this warning?
may be, but it's not necessary;
I need to fix this cause the simulation doesn't work correctly
if the simulation shows unexpected behavior the problem is somewhere else,
not in the bit tied to '0';

J.A
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
Re: WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

If you are worried that trimming is affecting things, then you can put a S (save) attribute on the FF's that are being trimmed.

Also see this xilinx AR... AR #23990 - 11.1 MAP - Master Answer Record for MAP Trimming Issues

But as pointed out, it is very likely that the simulation giving incorrect results is not caused by logic trimming, but by something else.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top