Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound

[sivarajm]

Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound

Hi,

I am trying to simulate a SIN and COS LUT table generated from core-gen.
1. I have created "Xilinxcorelib"
2. Corresponding files are compiled.
3. Wen I am simulating, I am getting this warning. (please refer "NOTE")

Give me some idea to clear this issue,


"NOTE" : Warning Msg

vcom -reportprogress 300 -work work C:/Xilinx/Projects/Coregen_LUT/slicelut.vhd
# Model Technology ModelSim SE vcom 6.3f Compiler 2008.02 Feb 28 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity slicelut
# -- Compiling architecture slicelut_a of slicelut
# -- Loading package std_logic_arith
# -- Loading package std_logic_signed
# -- Loading package numeric_std
# -- Loading package math_real
# -- Loading package textio
# -- Loading package bip_utils_pkg_v2_0
# -- Loading package bip_usecase_utils_pkg_v2_0
# -- Loading package xcc_utils_v2_0
# -- Loading package pkg_dds_compiler_v4_0
# -- Loading package dds_compiler_v4_0_sim_comps
# -- Loading package xbip_pipe_v2_0_xst_comp
# -- Loading entity dds_compiler_v4_0
vsim work.slicelut
# vsim work.slicelut
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_signed(body)
# Loading ieee.numeric_std(body)
# Loading ieee.math_real(body)
# Loading std.textio(body)
# Loading xilinxcorelib.bip_utils_pkg_v2_0(body)
# Loading xilinxcorelib.bip_usecase_utils_pkg_v2_0(body)
# Loading xilinxcorelib.xcc_utils_v2_0(body)
# Loading xilinxcorelib.pkg_dds_compiler_v4_0(body)
# Loading xilinxcorelib.dds_compiler_v4_0_sim_comps
# Loading xilinxcorelib.xbip_pipe_v2_0_xst_comp
# Loading work.slicelut(slicelut_a)#1
# Loading xilinxcorelib.dds_compiler_v4_0(behavioral)#1
# ** Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound.
# Time: 0 ns Iteration: 0 Region: /slicelut/u0/i_single_channel File: C:/Xilinx/Projects/Coregen_LUT/corefiles/dds_compiler_v4_0.vhd
# ** Warning: (vsim-3473) Component instance "i_pipe_phase_out : xbip_pipe_v2_0_xst" is not bound.
# Time: 0 ns Iteration: 0 Region: /slicelut/u0 File: C:/Xilinx/Projects/Coregen_LUT/corefiles/dds_compiler_v4_0.vhd
# ** Warning: (vsim-3473) Component instance "i_pipe_sin : xbip_pipe_v2_0_xst" is not bound.
# Time: 0 ns Iteration: 0 Region: /slicelut/u0/i_sincos/i_sincos_op_pipes/i_has_sine File: C:/Xilinx/Projects/Coregen_LUT/corefiles/dds_compiler_v4_0.vhd
# ** Warning: (vsim-3473) Component instance "i_pipe_cos : xbip_pipe_v2_0_xst" is not bound.
# Time: 0 ns Iteration: 0 Region: /slicelut/u0/i_sincos/i_sincos_op_pipes/i_has_cos File: C:/Xilinx/Projects/Coregen_LUT/corefiles/dds_compiler_v4_0.vhd[/SIZE]

 

[Sckoarn]

Re: Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound

sivarajm,
Looks like at some place, the library is not stated and used, or the modelsim.ini file does not map the xilinxcorlib to the place expected by /slicelut/u0.

Sckoarn

 

[sivarajm]

Re: Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound

Hi Sckoarn,

Thank you for your valuable reply.
Actually I copied all the supporting files and compiled. Even then, at the time of simulating I am facing this issue. I thought of missing some files initially so I have tried even more than thrice, but i am facing same issue. I dont think i am missing any files.
moreover I have experience on simulating the coregen files long back, at that time I was using ISE 10.1, recently i shifted to 12.4, in this i am facing this problem.

Can u tell me how to solve this issue or what mistake i am doing?
If u need i will also provide u screen shorts.
Let mi know if u need any other details of this issue.

 

[Sckoarn]

Re: Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound

sivarajm,

Where ever you have instantiated the cores, you need to have library and use statements. If you collected all the files and compiled them in "work" then library statements are not the issue. Modelsim should be looking in the work lib for anything it needs.

Are you sure you are using the correct names of the cores you want to use? You can check the entity of the core for the for sure real name.

There could be a port missmatch between component instatiation, port map and real core entity.

That is all I can think of at the moment.
feel free to post up some of the /slicelut/ code.

Sckoarn