DarkInsanePyro
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Hey guys so my semester is wrapping up and fortunately I have gotten all of the projects for the class done. Now this is a simple question. Xilinx is issuing a warning but it doesn't seem to be enforcing what it says. More specifically I have no idea why it is even stating it in the first place. The optimization warnings make sense since I zero-extend the inputs from 4-bit to 8-bit and it can just optimize away 4 bits of the bus. What I am wondering about is the first warning where u1's output seems to be disconnected. Simulation is proving that this system works fine though. I just want to make sure there isn't any issue I am overseeing because if it was really disconnected my project wouldn't work at all. I haven't had the opportunity to test on hardware yet and unfortunately due to other classes clashing on time I will be testing on the due date (terrible I know). So I'll find out then. I don't see why it wouldn't... simulation likes the setup.
Code:
--################################################################################
--# FullAdder
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
entity FullAdder is
port(
-- inputs
A, B, Cin : in std_logic;
-- outputs
Q, Cout : out std_logic
);
end FullAdder;
architecture FullAdder_RTL of FullAdder is
begin
Q <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end FullAdder_RTL;
--################################################################################
--# Adder
--# Width: 8-Bit
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
entity Adder is
generic(
Width : integer := 8
);
port(
-- inputs
A, B : in std_logic_vector(Width-1 downto 0);
Cin : in std_logic;
-- outputs
Q : out std_logic_vector(Width-1 downto 0);
CarryBus : out std_logic_vector(Width downto 0);
Cout : out std_logic
);
end Adder;
architecture Adder_RTL of Adder is
signal int_carry : std_logic_vector(Width downto 0);
signal int_result : std_logic_vector(Width-1 downto 0);
component FullAdder port (A,B,Cin : in std_logic; Q,Cout : out std_logic); end component;
begin
int_carry(0) <= Cin;
gen: for i in Width-1 downto 0 generate
fa: FullAdder port map(A=>A(i), B=>B(i), Cin=>int_carry(i), Q=>int_result(i), Cout=>int_carry(i+1));
end generate;
Q <= int_result;
Cout <= int_carry(int_carry'left);
CarryBus <= int_carry;
end Adder_RTL;
--################################################################################
--# DataBuffer (Register)
--# Width: 8-Bit
--# Reset: Async
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DataBuffer is
port(
-- inputs
D : in std_logic_vector(7 downto 0);
Clk : in std_logic;
Rst : in std_logic;
-- outputs
Q : out std_logic_vector(7 downto 0)
);
end DataBuffer;
architecture DataBuffer_RTL of DataBuffer is
signal state : std_logic_vector(7 downto 0);
begin
process (D,Clk,Rst)
begin
if (Rst = '1') then
state <= (others => '0');
elsif (Clk'event and Clk = '1') then
state <= D;
end if;
end process;
Q <= state;
end architecture;
--################################################################################
--# Accumulator
--# Width: 8-Bit
--# Clock: Rising Edge
--# Reset: Async
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Accumulator is
port(
-- inputs
D : in std_logic_vector(7 downto 0);
Clk : in std_logic;
Rst : in std_logic;
-- outputs
Q : out std_logic_vector(7 downto 0)
);
end Accumulator;
architecture Accumulator_RTL of Accumulator is
--------------------------------
-- required components
--------------------------------
component Adder is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
Q : out std_logic_vector(7 downto 0);
CarryBus : out std_logic_vector(8 downto 0);
Cout : out std_logic
);
end component;
--------------------------------
-- internal signals
--------------------------------
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal next_value : std_logic_vector(7 downto 0);
begin
-- components
u1: Adder port map (A=>value, B=>D, Cin=>'0', Q=>next_value);
-- logic
process (D,Clk,Rst)
begin
if (Rst = '1') then
value <= (others => '0');
elsif (Clk'event and Clk = '1') then
--value <= std_logic_vector(unsigned(value) + unsigned(D));
value <= next_value;
end if;
end process;
Q <= value;
end architecture;
--################################################################################
--# ZeroDetect
--# Width: 8-Bit
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
entity ZeroDetect is
port(
-- inputs
D : in std_logic_vector(7 downto 0);
-- outputs
Z : out std_logic
);
end ZeroDetect;
architecture ZeroDetect_RTL of ZeroDetect is
begin
Z <= not (D(0) or D(1) or D(2) or D(3) or D(4) or D(5) or D(6) or D(7));
end architecture;
--################################################################################
--# Decrementer
--# Width: 8-Bit
--# Clock: Falling Edge
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Decrementer is
port(
-- inputs
D : in std_logic_vector(7 downto 0);
Load : in std_logic;
Clock : in std_logic;
-- outputs
Q : out std_logic_vector(7 downto 0);
Z : out std_logic
);
end Decrementer;
architecture Decrementer_RTL of Decrementer is
--------------------------------
-- required components
--------------------------------
component Adder is port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
Q : out std_logic_vector(7 downto 0);
CarryBus : out std_logic_vector(8 downto 0);
Cout : out std_logic
);
end component;
component ZeroDetect is port (
D : in std_logic_vector(7 downto 0);
Z : out std_logic
);
end component;
--------------------------------
-- internal signals
--------------------------------
signal value : std_logic_vector(7 downto 0);
signal dec_value : std_logic_vector(7 downto 0);
begin
-- logic
process (Load, Clock, D)
begin
if (Load'event and Load = '1') then
value <= D;
elsif (Clock'event and Clock = '0') then
value <= dec_value;
end if;
end process;
-- components
u1: Adder port map (A=>value, B=>"11111111", Cin=>'0', Q=>dec_value);
u2: ZeroDetect port map (D=>value, Z=>Z);
Q <= value;
end architecture;
--################################################################################
--# Multiplier
--# Width: 4-Bit x 4-Bit = 8-Bit
--# Start: Rising Edge
--# Load: Rising Edge
--# Clear: Async
--################################################################################
library ieee;
use ieee.std_logic_1164.all;
entity Multiplier is
port(
-- inputs
A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
Load : in std_logic;
Start : in std_logic;
Clear : in std_logic;
Clock : in std_logic;
-- outputs
Product : out std_logic_vector(7 downto 0);
Run : out std_logic
);
end Multiplier;
architecture Multiplier_RTL of Multiplier is
--------------------------------
-- Predefined Entities
--------------------------------
component DataBuffer port (
D : in std_logic_vector(7 downto 0);
Clk, Rst : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component;
component Accumulator port (
D : in std_logic_vector(7 downto 0);
Clk : in std_logic;
Rst : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component;
component Decrementer port (
D : in std_logic_vector(7 downto 0);
Load : in std_logic;
Clock : in std_logic;
Q : out std_logic_vector(7 downto 0);
Z : out std_logic
);
end component;
--------------------------------
-- Internal Signals
--------------------------------
signal a_extended : std_logic_vector(7 downto 0);
signal b_extended : std_logic_vector(7 downto 0);
signal a_value : std_logic_vector(7 downto 0);
signal b_value : std_logic_vector(7 downto 0);
signal run_clock : std_logic;
signal b_zero : std_logic;
signal running : std_logic := '0';
begin
-- components
u1: DataBuffer port map (D=>a_extended, Clk=>Load, Rst=>'0', Q=>a_value);
u2: Decrementer port map (D=>b_extended, Load=>Load, Clock=>run_clock, Z=>b_zero); -- falling edge clocked
u3: Accumulator port map (D=>a_value, Clk=>run_clock, Rst=>Clear, Q=>Product); -- rising edge clocked
-- logic
run_clock <= Clock and (not b_zero) and running; -- only run for as long there is a value in B
a_extended <= "0000" & A;
b_extended <= "0000" & B;
process (b_zero, running, Start, Clock)
begin
-- start the process if:
-- 1. Start signal asserted (rising edge)
-- 2. Latched B value is larger than zero.
if (Start'event and Start = '1' and (b_zero = '0')) then
running <= '1';
end if;
-- stop the process if
-- 1: B value is zero
if (Clock = '0' and (b_zero = '1')) then
running <= '0';
end if;
end process;
Run <= running;
end architecture;
