This was one of my projects last quarter, we used an Alexander phase detector (full rate), V/I converter (can be found in one of Razavi's papers), LC VCO. I don't think this is good enough for a company though, as there is not much frequency detection. We used CML based circuits driven with ~1mA, 0.18u technology.
I am actually impressed that any company is will ing to start with that. Usually there are well established players already.
As far as topology I would recommend LC tank VCO , prescaler would be differential, counters should be sE to cut down the power, 2nd order should make it for you but depends what is your spec.
In general 0.18um should be enough for it. Or any BiCmos with ft 15GHz should make it.
actually, it is an academic project.
from my simulation, the Vctrl of VCO is not stable, depending on the incomming data signals.
is the dual loop (another loop of freqency detector) a must?
and i cannot find the schematic of frequency detector. anyone has the schematic?
I adopt the dual loop half rate CDR w/ reference clock, my coarse loop is a low
speed pll , I just use a TSPC type logic cell like D-FF and NOR to build the PFD
Maybe you wanna use a referenceless arch.
Would you mind sharing your arch. ?
yes, my schematic is similar, using I and Q of quadrature VCO.
i find that when there is too long consecutive ZERO, the CDR can not synchronize well. i think it is not real case, I have to make sure the inputting signal has fewer consecutive ZEROs.
The Max. number of consecutive identical digits of 8B/10B coding is 5 bits
I think it is not a problem for synchronization error.
If you need to tolerate more than 5 bit or very long CID, maybe you need the
2nd pll loop and lock detector to keep synchronization under CID period.