want to design a 2.5Gbps CDR

[beabroad]

hi all

i just want to design a 2.5Gbps CDR. i want to make the power consumption as low as possible.

any idea of that?

i read some books and papers, and find the recent papers are on 10G and 40G. most are quadrature or half-rate.

i want to know which kind of topology a company may choose.

many thanks.

 

[easytarget]

This was one of my projects last quarter, we used an Alexander phase detector (full rate), V/I converter (can be found in one of Razavi's papers), LC VCO. I don't think this is good enough for a company though, as there is not much frequency detection. We used CML based circuits driven with ~1mA, 0.18u technology.

 

[beabroad]

regarding to the loop filter, did you use 3rd order or 2nd order?
in my simulation when using 3rd order, i find the Vreq is not stable

some papers use dual loop, with the other loop using frequency detector. i wonder whether it is a must to add such loop in the cdr circuit.

 

[Teddy]

I am actually impressed that any company is will ing to start with that. Usually there are well established players already.
As far as topology I would recommend LC tank VCO , prescaler would be differential, counters should be sE to cut down the power, 2nd order should make it for you but depends what is your spec.

In general 0.18um should be enough for it. Or any BiCmos with ft 15GHz should make it.

 

[beabroad]

actually, it is an academic project.
from my simulation, the Vctrl of VCO is not stable, depending on the incomming data signals.
is the dual loop (another loop of freqency detector) a must?
and i cannot find the schematic of frequency detector. anyone has the schematic?

 

[jxzhang]

What's ur N for ur divider in the coarse loop(freq locking)?

 

[beabroad]

currently, i did not use frequency locking loop. that may be the problem.

 

[jxzhang]

I adopt the dual loop half rate CDR w/ reference clock, my coarse loop is a low
speed pll , I just use a TSPC type logic cell like D-FF and NOR to build the PFD
Maybe you wanna use a referenceless arch.
Would you mind sharing your arch. ?

 

[beabroad]

the schematic is as follows:
Alex_PD -> charge pump - > 3rd order LP -> LC VCO
maybe i shall use 2nd order LP instead of 3rd order?

and where i can find the schematic of frequency locking detector? no paper exactly gives the schematic.

 

[jxzhang]

ur VCO have to output CK phase I and Q
building these D-FF by CML

 

[beabroad]

yes, my schematic is similar, using I and Q of quadrature VCO.
i find that when there is too long consecutive ZERO, the CDR can not synchronize well. i think it is not real case, I have to make sure the inputting signal has fewer consecutive ZEROs.

 

[jxzhang]

The Max. number of consecutive identical digits of 8B/10B coding is 5 bits
I think it is not a problem for synchronization error.
If you need to tolerate more than 5 bit or very long CID, maybe you need the
2nd pll loop and lock detector to keep synchronization under CID period.