Want know some tips about gated clock

[Ansunamu]

I am trying to design a MCU with gated clock to save the power . I have no idea about how to write the script to synthesis my chip

Because the AND or NAND gate used to gate the clock has a long delay but it not make sense since the clock tree has not been created .

The Clock tree will be created by P&R tool and the delay of these gate used to gate the clock should be short . I already tried to run the postlayout simulation and the delay of the gate is what i expected .

I am wondering that i must can write the good synthesis script to generate a right SDF file

Does anyone have any idea about that ?

 

[philewar]

I think checking DC's manual will help a lot.

 

[sandusty]

put don't touch on your high fanout nets (for example, clocks). Run pre-sim with modified sdf (from pt or dc). You have nothing to do on the synthesis scripts for the pre-sim sdf.

Let the Backend tools generated the clock tree(s) for you, and than got the more precise SDF for the post-sim.

 

[maniasonic]

if you have PowerCompiler you can have it done much more easily.