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W/L ratio and reason for weak pull-up transistor in CMOS SRAM design

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weng

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Hi,

I face some problems in designing a full CMOS SRAM cell:

1. The choose of W/L ratio
The W/L of the back-to-back inverters should be the same? I saw this in somewhere. I was confuse by that because in a latch, the forward inverter should be stronger than the feedback inverter...
The Wordline transistor should have smaller W/L compare to back-to-back inverter?
How bout the Bitline transistor?

2. Why there is a need of weak pull-up transistor?
 

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