Vref for LVDS pin assignment

[imbichie]

Hi All,

I am working with Lattice ECP2 FPGA. In my design i need to connect the input and output ports to "LVDS25" I/O interface.
The thing is shall i specify or assign any Vref to the bank which contains my LVDS ports ?...

I had tried the design without Vref but the its not working...
Another thing is that when i assign the ports as "LVTTL33" its working fine...

But when i changed the ports to "LVDS25" its not working ?

Thanks in Advance....

 

[lucbra]

The procedure is as follows:

In Diamond (or ispLever), after compiling the design, open the spreadsheet view, assign your LVDS signal to the positive of an LVDS capable pin. If the signal is an output, there is no need for the Vref. When the signal is an input, then you will need to bring 1.25V to the Vref pin of the resp bank. That should work.
The negative pin is assigned automatically.

 

[imbichie]

Thank You for your reply...

But one thing i noted is that in the ECP2 datasheet they specify that we no need to assign any Vref for LVDS and all, Vref is need for SSTL, etc...

Another thing in my design is that the VCCIO of the bank which contain the LVDS25 port is 3.3V...
Should it be 2.5V...?

Thanks in Advance..

 

[lucbra]

First of all, does it work well now? If it doesn't, we need to dig deeper.

And yes, the VCCIO should be 2.5V if you want to interface with existing equipment. If the interface is set up between 2 similar ECP2 devices, it shouldn't be a big problem (as the inputs and outputs are 3.3V tolerant)