Voltage error of pipeline ADC !

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hi all:
for pipeline ADC ,1LSB total voltage error (refered back to ADC input ) is enough for monotonicity . to reliably guarantee monotonicity ,1/2LSB is specified ,this also means each individual stage should be designed to have a total voltage error less than 1/4 LSB of the effetive resolution of the remaining stages. how can i get the second meaning ? thanks !
related paper :
 

I not sure but may be it comes from this:

e1 + e2 / 2 + e3 /4 + ... < 0.5LSB
if e1=e2=... =e
e(1+1/2+1/4+...)<0.5LSB
2e<0.5LSB
e<0.25LSB

Added after 7 minutes:

There are some papers on this subject, e.g. :
S.H. Lewis, TCAS-II, Aug. 1992
P.J. Quinn, ISCAS, 2005

However error is a tricky subject! it is better to talk about INL and DNL.

Added after 42 minutes:

The second paper (the one you linked to) is somehow vague. For example equ. (11) comes from nowhere!. I you get it pls let me know.
 

thank you.
do you know how to get the second meaning of " each individual stage should be designed to have a total voltage error less than 1/4 LSB of the effetive resolution of the remaining stages"
 

Here is the name of two good references:
1. S.H. Lewis, Optimizing the stage resolution in pipelined, multistage, ... , TCAS-I, Aug. 1992

2. A.M. Abo, Design for Reliability of Low-voltage,
Switched-capacitor Circuits, Phd thesis, UC Berkeley, 1999
 

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    jeniffer

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