You probably don't have a static design: this would mean you'd have to find a worst case simulation concerning net voltages (or determine these min. and max. net voltages manually). Then you'd have to write a SKILL program, which assigns these min. and max. net voltage values as properties to the respective nets, then one more SKILL routine, which e.g. creates a new layer structure for layer_net_difference >=3V . Then, standard DRC rules with a logical AND combination can decide on the nets' spacing.
I don't know if newer DRC programs can already use logical decisions not only based on physical (geometrical) dimensions, but perhaps also on net properties. This would spare the 2nd SKILL program.
Of course only nets on the same layer would be affected - you can't change the spacing between nets on different layers.
For a real design I'd never use such a layout complication, would use a global max. spacing. But I admit, this could be a nice academic task.
Good luck!