Voltage and cell delay of a cell (STA)

[angadir]

Hi Everybody!

Can sombody telme why is that the cell delay reduces when the voltage increases?

When we consider cell delay in STA. PVT factors...Which is the most dominating factor of these three and what are their percentages in terms of influence on cell delay?


Thanks
Ravi

 

[natg9]

hi friend

in my knowledge there is no such a thing that u calculate the effect of PVT individually


The various effects are calculated considering all three ie process ,voltage and temperature and a coeeficient is calculated which is used for calculation in the efffects it causes on the timing

based on the best , typical, worst PVT values we have a coefficient K that is applied to the timing stat

regarding the cell delay and voltage relation
please read some semiconductor physics basic theory on effects of increasing voltage on mobility electrons and holes


correct me if i am wrong

Added after 2 hours 9 minutes:

here are some graphs that would be helpful

 

[angadir]

Hi friend,

I do have this info...but what I m looking for is the detailed explaination for each of these PVT factors. And their % of contribution in determining the delay of the cell.

Thanks,
Ravi

 

[natg9]

Hi ravi

i told u in my opinion u cant have individual effects known
Also these are specified by the foundry so each foundry may have their own chart

well this is what i know

incase u get some info then please correct me

bye

 

[mfengwu]

Normally, increase the voltage, the cell will run fast, so the delay change small.
for the temperature, high temperataure will inclease the delay value.
So in 90nm, 130nm and above, the corner is defined as follows:

Best case: High V, Low T(0 centi degree),
Typical case: Norm V, Norm T(25 centi degree);
Worst Case: Low V, High T(125 centi degree);

But in the 65nm, 45nm, and below, there is temperature inversion.
that is lower temperature(-25) will have larger delay than the 125 temperature. so in the 65nm and below, another corner is added for simulation

 

[Amruth]

hi,

for standard cell design the process is same but we have different voltage and temp i.e,min and max. but u r design has to work in all circumstances so u need to verify u r cell timing in different variations. so delay is impacted by all variables we cant say the percentage of contribution.

 

[Anbusivam]

Hi,

Can you tell me what is the additional corner added to take care Temp Inversion during the Design in 45nm.


Thank for your time.

Regards,
Anbusivam