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VLSI Simulation in PSPICE AD

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esrahul

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I would like to add my VHDL Design as a Component in PSPICE and Simulate it with the help of already available models. I assigned the VHDL file to an Hierarchical Model. But during simulation its failed to give the output, thd default output was xx. I think I made mistake on giving supply for the VHDL Design Model. Can anyone suggest how to simulate our VHDL core in PSPICE??

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