Nixphe
Junior Member level 1
Hello
i use layout xl to draw the designs of my schematics. During layout, sometimes i make small changes to my schematic or i add some decoupling or so. Imagine i take a transistor. During layout i add it in my schematic with S and D to VDD! and bulk and gate to GND!. I "update source", and I can pick the new device from schematic. However, i notice i'd better put S and D and bulk to GND and gate to VDD! for some reason. None of the update or check functions in the connectivity menu seem to be able to make Layout XL aware of the change. For the remaining of my layout it complains about those connections only.
Does anyone have a solution for this?
Second small question: in my schematics i use inherited nets, Vdd*, GND*. Layout XL requests me to denote my pins as "Vdd!" and "GND!" and my Calibre LVS tool wants me to call them Vdd and GND. Is there a workaround for this? I'd like Calibre LVS and Layout XL to accept the same notation.
Thanks for your help!
Nixphe
i use layout xl to draw the designs of my schematics. During layout, sometimes i make small changes to my schematic or i add some decoupling or so. Imagine i take a transistor. During layout i add it in my schematic with S and D to VDD! and bulk and gate to GND!. I "update source", and I can pick the new device from schematic. However, i notice i'd better put S and D and bulk to GND and gate to VDD! for some reason. None of the update or check functions in the connectivity menu seem to be able to make Layout XL aware of the change. For the remaining of my layout it complains about those connections only.
Does anyone have a solution for this?
Second small question: in my schematics i use inherited nets, Vdd*, GND*. Layout XL requests me to denote my pins as "Vdd!" and "GND!" and my Calibre LVS tool wants me to call them Vdd and GND. Is there a workaround for this? I'd like Calibre LVS and Layout XL to accept the same notation.
Thanks for your help!
Nixphe