go4sandesh_vsn
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hi....i m facing problems synthesizing dpRAM (with both ports reading as well as writing).......
i m giving my code here
here i m using a single process for both clocks.....i hav tried using different processes also...but its not synthesizeable
kindly help
[/quote]
plz take care I m writing frm both the ports(here i hav removed the logic when there is a conflict i.e. when both ports want to write at the same location....this i did to simplify the logic coz even with the old code i was not able to synthesize it)
i m giving my code here
here i m using a single process for both clocks.....i hav tried using different processes also...but its not synthesizeable
kindly help
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
--ENTITY DPRAM16x9
-------------------------------------------------------------------------------
entity dpRam16x9 is
port
(
reset : in std_logic; -- Asynchronous RESET
clk_A : in std_logic; -- Port A clock(input)
clk_B : in std_logic; -- Port B clock(input)
Addr_A : in std_logic_vector(3 downto 0);-- Port A Address(input)
Addr_B : in std_logic_vector(3 downto 0);-- Port B Address(input)
Wr_en_A : in std_logic; -- Write Enable of Port A(input)
Wr_en_B : in std_logic; -- Write Enable of Port B(input)
Din_A : in std_logic_vector(8 downto 0);-- Data IN of Port A(input)
Din_B : in std_logic_vector(8 downto 0);-- Data In of Port B(input)
Dout_A : out std_logic_vector(8 downto 0); -- Read Data of Port A(output)
Dout_B: out std_logic_vector(8 downto 0) -- Read Data of Port B(output)
);
end dpRam16x9;
-------------------------------------------------------------------------------
--ARCHITECTURE of dpRam16x9 begins here
-------------------------------------------------------------------------------
architecture dpRam16x9_beh of dpRam16x9 is
type Ram is array(15 downto 0) of std_logic_vector(8 downto 0);
signal dpRam:Ram;
signal rd_addr_A,rd_addr_B:std_logic_vector(3 downto 0);
begin
PortA_P:process(clk_A,clk_B)
begin
if reset ='1' then
dpram<=(others=>(others=>'0'));
else
if(clk_A'event and clk_A='1') then
if wr_en_A='1' then
dpRam(conv_integer(addr_A))<= Din_A;
end if;
end if;
if(clk_B'event and clk_B='1') then
if wr_en_B='1' then
dpRam(conv_integer(addr_B))<= Din_B;
end if;
end if;
end process;
Dout_A<=dpRam(conv_integer(addr_A));
Dout_B<=dpRam(conv_integer(addr_B));
end dpRam16x9_beh;
plz take care I m writing frm both the ports(here i hav removed the logic when there is a conflict i.e. when both ports want to write at the same location....this i did to simplify the logic coz even with the old code i was not able to synthesize it)