virtex 2 .... dpRAM with dual writes

[go4sandesh_vsn]

hi....i m facing problems synthesizing dpRAM (with both ports reading as well as writing).......

i m giving my code here
here i m using a single process for both clocks.....i hav tried using different processes also...but its not synthesizeable

kindly help

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-------------------------------------------------------------------------------
--ENTITY DPRAM16x9
-------------------------------------------------------------------------------
entity dpRam16x9 is
  port
    (
      reset   : in std_logic;           -- Asynchronous RESET
      clk_A   : in std_logic;                   -- Port A clock(input)
      clk_B   : in std_logic;                   -- Port B clock(input)
      Addr_A : in std_logic_vector(3 downto 0);-- Port A Address(input)
      Addr_B : in std_logic_vector(3 downto 0);-- Port B  Address(input)
      Wr_en_A : in std_logic;                   -- Write Enable of Port A(input)
      Wr_en_B : in std_logic;                   -- Write Enable of Port B(input)      
      Din_A     : in std_logic_vector(8 downto 0);-- Data IN of Port A(input)
      Din_B     : in std_logic_vector(8 downto 0);-- Data In of Port B(input)      

      Dout_A : out std_logic_vector(8 downto 0);   -- Read Data of Port A(output)
      Dout_B: out std_logic_vector(8 downto 0)   -- Read Data of Port B(output)
      );
end dpRam16x9;

-------------------------------------------------------------------------------
--ARCHITECTURE of dpRam16x9 begins here
-------------------------------------------------------------------------------
architecture dpRam16x9_beh of dpRam16x9 is
  type Ram is array(15 downto 0) of std_logic_vector(8 downto 0);
  signal dpRam:Ram;
  signal rd_addr_A,rd_addr_B:std_logic_vector(3 downto 0);
  
  begin
  
  PortA_P:process(clk_A,clk_B)                 

    begin

      if reset ='1' then
        dpram<=(others=>(others=>'0'));
       
      else
        if(clk_A'event and clk_A='1') then
          if wr_en_A='1' then
               dpRam(conv_integer(addr_A))<= Din_A;
          end if;
       end if;
               
       if(clk_B'event and clk_B='1') then
         if wr_en_B='1'  then
             dpRam(conv_integer(addr_B))<= Din_B;
         end if;
       end if;

      end process;
      
      Dout_A<=dpRam(conv_integer(addr_A));   
      Dout_B<=dpRam(conv_integer(addr_B));

      
  end dpRam16x9_beh;

[/quote]



plz take care I m writing frm both the ports(here i hav removed the logic when there is a conflict i.e. when both ports want to write at the same location....this i did to simplify the logic coz even with the old code i was not able to synthesize it)

 

[echo47]

I tried your code in both ModelSim 6.2a and ISE 8.1i, and both are giving syntax errors. Which software are you using?

I don't know VHDL very well, but maybe my Verilog hints will help you. In ISE 8.1i the XST Verilog compiler won't infer a two-port block RAM with both ports writing if I put everything into one Verilog "always" block. (I think a Verilog "always" is similar to a VHDL "process".) However, if I separate them as shown below, XST generates a nice block RAM. This also lets me use two separate clocks if I want to.

I haven't tried two-port writing until now, but XST's behavior smells like a limitation/bug. Maybe 8.2i is smarter.

If you are still stuck, you can forgo HDL inference and simply instantiate a RAMB16_S18_S18 library part. That always works.

module top (clkA, clkB, idataA, idataB, addrA, addrB, weA, weB, odataA, odataB);
  input             clkA, clkB;
  input       [7:0] idataA, idataB;
  input       [9:0] addrA, addrB;
  input             weA, weB;
  reg         [7:0] ram [0:1023];
  output reg  [7:0] odataA, odataB;

  always @ (posedge clkA) begin
    if (weA)
      ram[addrA] <= idataA;
    odataA <= ram[addrA];
  end
  always @ (posedge clkB) begin
    if (weB)
      ram[addrB] <= idataB;
    odataB <= ram[addrB];
  end
endmodule

 

[vibhute_r_p]

There are several model codes avaliable in xst user manul of xilinx. For dual port ram with two read + write ports there is a code. If you use that with ise , i am sure it will give you dual port ram. How ever same codee i tried with synplify pro. It is giving error "No such flipflop exists". In such a case it is recomanded that use coregen or use instance of RAMB_S**_S** where ** depends upon your data width.

Regards,
Ram

 

[echo47]

Thanks vibhute_r_p. I somehow couldn't find that example when I wrote my earlier message, but now I see it. Search the XST User Guide for "Dual-Port Block RAM with Two Write Ports". The examples include VHDL and Verilog. The Verilog example is similar to mine, but includes the enable inputs.

It also has the same weird problem I mentioned earlier. If I use one clock and one Verilog "always" block, ISE 8.1.03 infers distributed RAM instead of block RAM. I found a somewhat-related answer record that suggests this may be fixed in ISE 9.1i.

 

[go4sandesh_vsn]

yup thnx buddy.....
well as i found out its not possible to write this model with dual write ports (DPRAM)each having independent clocks....as a flop can't have two clocks......
but i suppose it can be done by use of latches......if anybody has any idea...do share it......

else u can direcly instantiate if u need it.....right
thnx once again......

 

[echo47]

Don't give up yet! Did you try my Verilog example above, or the VHDL/Verilog example that vibhute_r_p mentioned in the XST User Guide? They both have independent clocks and dual write ports, and synthesizes fine with XST.

There should be no flops here, only the block RAM.

Are you using XST, or some other synthesizer? XST is sometimes smarter than other synthesizers.

 

[bansalr]

the VHDL code seems to be fine.
Can u just check that the simulator is compliant to VHDL 2004 stanadrd compliance.
even this code shall be synthesizable and shall understand which clock to take for which flops rather than writing two different process.

 

[vibhute_r_p]

Hi,

so far i know from book designs warrirs guide to fpgas, gate cound for latches is less that flip flops. So the fpgas will generally designed with latches with some wrapper to use them as flipflop.

will any body come with code where latches are used for dp ram and the wrapper around it makes it behave like flips at the intarface.


regards,
vibhute

 

[go4sandesh_vsn]

yup buddy.....
if anyone can come out with Latch based DPRAM that'll b gr8......

i've used this model with leonardo ....as well as with Xilinx 5.2.....but couldn't get it with that.........n didn't try much due to other stuffs.........

so looking 4 someone to really come up with a goood code......\

thnx 2 all of U guyz

 

[echo47]

I'm not sure exactly what you mean by "latch-based RAM", but the Block RAMs and Distributed RAMs provided for you in a Xilinx FPGA are faster and more compact than any kind of RAM you build yourself in the logic fabric.