VHDL vs Verilog which more popular?

[nitr8]

SystemVerilog supports the built-in C types to provide a clear translation to and from C for better encapsulation and code compaction. The C types also give users improved methods to create algorithmic models and advance the abstract syntax a designer can use to create efficient synthesizable code. Other synthesis improvements include enhancements to the “always” block to avoid simulation and synthesis mismatches. With SystemVerilog, designers can also specify intent with their simulation, synthesis and formal verification tools.

To enhance design verification, SystemVerilog adds four procedural assertions, which allows the designer to test Boolean expressions and perform an action based on the expression’s (or sequence of expressions’) value (true or false). Assertions can be added to the design to document the assumptions made by the designer and to facilitate “white box” testing. Assertions can also be outside the design, either in a testbench to check the response of the design to the stimulus, or to control a tool such as a stimulus generator or a model checker.

To improve modeling at the abstract level, SystemVerilog adds interfaces to help model the communication between blocks of a digital system. Communication between blocks of a digital system is a critical area that can affect everything from the ease of RTL coding, to hardware-software partitioning to performance analysis to bus implementation choices and protocol checking.

SystemVerilog’s interface construct was created to encapsulate the communication between blocks, allowing a smooth migration from abstract system-level design to lower-level register-transfer and structural views of the design. By encapsulating the communication between blocks, the interface construct facilitates design reuse.

 

[Jackal]

Yes, VHDL is popular in many European countryes. For example in Russia
about 70% of hardware programmers use VHDL, about 28% use AHDL and 2% is Verilog

But i think that we are must know both VHDL & Verilog and AHDL too )
But Verilog is most popular for design digatal ASIC's...

I usually use VHDL, and convert some sources from AHDL & Verilog in VHDL.

 

[gezzas525]

VHDL is much more flexible and mor robust than verilog especially when it comes to generics.

KLEOS

 

[eda_wiz]

hi,
vhdl is more popular.. Most universities have vhdl courses .. and not verilog.. people say verilog is easier than vhdl.. but idont think so.. if u r good in C .. verilog might be easier for u

 

[skynet]

VHDL only used in the academic for education purpose, while verilog used in Industry for commercial purpose. That make both of them different. Another thing is more and more eda tools had been design extensively based on verilog, where the systemC and also systemverilog for system level design.

 

[radix]

As was stated in previous replies, for the most part Verilog is more popular in the US, while VHDL is more popular outside the US.

The exception within the US is the govt and govt contractors, which still lean more toward VHDL.

If you learn VHDL first, it's probably easier to learn Verilog later. Most people that I've known that went from Verilog to VHDL really disliked it because it's more verbose and strict.

Radix

 

[srik]

IMO verilog is very easy to learn and use

look at this:

**broken link removed**

bye
srik

 

[verilog]

As I known, the leading IC insdustry is in the US. They are almost using Verilog. I am using Verilog too.

 

[dingo]

I understand that VHDL is used at universities and Verilog is used at
private companies.

Here at my university, nobody uses Verilog (that I know of), while VHDL is
a normal course that you can take.

 

[hynix]

VHDL vs Verilog

I think Due to powerfull contruct for digital logics VHDL is most popularly used for synthesis design & due to high flexibility for programming like C ,verilog is mostly used for writing behaveoral models,
-avinash

 

[PigiPigi]

It is very difficult to prefer one off them. If you want design a large and complex system, i recommend you to use VHDL. But if you want to design small things, i recommend you Verilog. I think with incoming large system design in future VHDL is successful in this area. Also SystemC is a new language with greater capability, that may overcomes to others.

 

[leonqin]

It is no use to talk about it.
Vhdl and VerilogHDl both can do the same thing

 

[azerm]

Each of VHDL or Verilog has its own advantages, and also it depends on softwares you use. For example in Cadence flow, Verilog is more useful.

But there are some other selections like SystemC, or in the future, SystemVerilog. It seems that these languages have good growth in the professional usage market of HDL languages.

 

[snakebites]

I think we should set up a vote to see which language is more popular.

 

[leonqin]

support!

 

[darkness]

VHDL vs Verilog

It is very difficult to prefer one of them. I think VHDL was born in the military area, so it is more oriented to the specification and definition, while Verilog was born in industries so it is "time-to-market" oriented.

 

[gladiolus]

Verilog or VHDL

In my experience with large companies - both VHDL and Verilog are used and supported. Design by design depending on your group you could be using one or the other.

Gladiolus

 

[vaf20]

i think VHDL in simulation is better,but verilog in synthesis

 

[asterix91]

Verilog Being more closer to C is easier to learn,
Whereas VHDL Forces the user to use stricter datatypes
and methodologies

 

[rewkie]

I think Verilog is easy to learn,but VHDL is precise.