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VHDL vs Verilog which more popular?

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Feb 6, 2002
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Which most prefer or popular? VHDL or Verilog?

On 2002-03-09 18:13, cadb0y wrote:
Which most prefer or popular? VHDL or Verilog?

Even a lot of large company still use both of them, depends on the projects. So both are popular, but seems Verilog is tend to be used more in the future?

I have found the reverse more VHDL, but certainly not one OR the other, tools support modules of either also ..

On 2002-03-11 05:23, TheMick wrote:
I have found the reverse more VHDL, but certainly not one OR the other, tools support modules of either also ..

VHDL is quite good in maintanance and Verilog nice to design so ... snip or snap

IMHO, I think Verilog will probably become increasingly dominant in the future. Realistically though, VHDL is here to stay for a long time. This means several things.

1) You still need to own and know how to use VHDL tools.

2) You still need to know VHDL

We happened to be interviewing ASIC designers lately. The interesting thing is, the younger the candidate is, the more likely he knows VHDL better than Verilog. I guess recently more schools in US are offering VHDL courses than Verilog. It would be interesting to see which language dominates in 5 years.

I am much surprised. Verilog looks more popular, good news for VHDL programmers :smile:

Whichever one gets adopted by the Analog design/synthesis tool developers will probably become the dominant one, then again they both will probably get used and we'll be right back where we started.

for HDL language programmers all over the world

VHDL approx 55%
Verilog approx 40 %
other HDL language 5%

but i think VHDL is easier to use
especailly for synthesizable logic

VHDL is by far more similar to a normal structured programming language (much like C) -- why when I read Verilog source code instead it gives me a strong impression of being little more than a plain-text netlist generated by some schematic capture?!?
Comments are welcome.

When you think the design hierarchy, VHDL maybe covers more the upper (higher abstarction level) part of scale, than Verilog, which is more suited/friendly to harware-close approach (RTL level). But both languages can do essentially everything.

An other difference is that VHDL is qute ADA like, strongly structured and more formal, while Verilog is maybe more related to C-language, and less verbose. And as most C programmers know, in C you can either write the mess you please, or make it structured - and the language/compiler allows both! (But a "clever" guy can write a mess in ANY language ) :smile:

Because both are extremely popular, and have each some (mariginal?) benefits, most likely they will both stay around for a long while.

I personally had to make recently a desicion which language to use for my next project, and it will be VHDL. It was not an obvious desicion, i still dislike the verbosity of VHDL, but appreciate it's structure!

I believe, that you can select the one which you like most, and which best covers your short-to-medium term needs, and it will be OK to use for several years!

Good luck,

thank you all, i much appreciate comments :smile:

Let me see it from another angle.

Have a search at amazon or fatbrain about VHDL and Verilog publications, VHDL books are published more so far.

However, I personally like Verilog as the way I prefer C more than Pascal.


VHDL ofcourse !!!

VHDL is more popular in academic, but not in the industry.

If you have to choose,

For school project => whichever one is OK.

For industrial use => Definitely choose verilog. Or you will have a lot of trouble synthesis, back annotation, linking with other tools....

It's not the problem of the language itself. Currently, it's the tool support. Not mature for VHDL.

<font size=-1>[ This Message was edited by: stevepre on 2002-04-26 04:29 ]</font>

I strongly agree with stevepre.
When using VHDL to finish a project, I have many problems in transfering data from one tool to another. So at last I have to use verilog in design.

But if I can choose, I will use VHDL.

Hi Jeck,

I am kinda curious to know what's on your mind. Why do you still want to choose VHDL after you have been through all this trouble with it?

<font size=-1>[ This Message was edited by: stevepre on 2002-04-26 04:30 ]</font>

>Anyway, why do you still want to choose VHDL?

U'r right about the VHDL. It (VHSIC) has been implemented first by the US military. Due to some unknown reason the military contractors favor ADA and that's where the dog is buried in when the VHDL get's conceived. Naturally like the most of the mil stuff, the VHDL is overbloated.

I started on VHDL because of my first project had to deal with some "reimplementation" of a VHDL code. It has been painfull to even switch to a different synthesis tool, due to the frivolous typecasting. Now I use verilog and the life is much easier, the code is much compact, cleaner and easier to follow :smile:

Then the verilog is not a static standart. In it's new incarnation it implements some nice structural features too (just follow the comitee anouncements)

Anyway in terms of available sourcecode for download, the VHDL is far more represented, but that's why XHDL comes very usefull from time to time :smile:

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