-- P_TTL_GEN: TTL signals are gated with the result of the time interpolated unit
-- and the Hamming window readings.
P_TTL_GEN: process(i_clk)
begin
if (i_clk'event and i_clk = '1') then
if (i_rst = '1') then
s_ttl_cnt_p <= (others => '0');
s_ttl_cnt_n <= (others => '0');
s_tx_n <= '1';
s_tx_p <= '0';
s_p_cnt_set <= '0';
s_n_cnt_set <= '0';
else
-- tx_p generation
if (s_tx_cr_p_zc = '1') then -- Chirp sine rising edge
s_ttl_cnt_p <= (others => '0');
s_tx_p <= '0';
s_p_cnt_set <= '1';
elsif (s_p_cnt_set = '1') then
if (s_ttl_cnt_p < s_ttl_high) then
s_ttl_cnt_p <= s_ttl_cnt_p + 1;
s_tx_p <= '1';
else
s_p_cnt_set <= '0';
s_tx_p <= '0';
end if;
end if;
-- tx_n generation
if (s_tx_cr_n_zc = '1') then -- Chirp sine falling edge
s_ttl_cnt_n <= (others => '0');
s_tx_n <= '0';
s_n_cnt_set <= '1';
elsif (s_n_cnt_set = '1') then
if (s_ttl_cnt_n < s_ttl_high) then
s_ttl_cnt_n <= s_ttl_cnt_n + 1;
s_tx_n <= '1';
else
s_n_cnt_set <= '0';
s_tx_n <= '0';
end if;
end if;
end if;
end if;
end process P_TTL_GEN;
signal s_ttl_high : unsigned(14 downto 0);
signal s_ttl_cnt_n : unsigned(s_ttl_high'range);
signal s_ttl_cnt_p : unsigned(s_ttl_high'range);
-- P_TTL_HIGH: This product determines the % of TTL pulses within one
-- period or the time that the PWM is high within one period.
P_TTL_HIGH: process(i_clk)
begin
if (i_clk'event and i_clk = '1') then
if (i_rst = '1') then
s_ttl_high_sfx <= (others => '0');
elsif (s_ttl_data_hi_rdy = '1') then
s_ttl_high_sfx <= s_wdw_high_sfx*s_ttl_tunit_high_sfx ;
end if;
end if;
end process P_TTL_HIGH;
P_TTL_HIGH_CONV: PROCESS(i_clk)
begin
if (i_clk'event and i_clk = '1') then
s_ttl_high <= to_unsigned(to_integer(s_ttl_high_sfx(s_ttl_high_sfx'left downto 0)),s_ttl_high'length);
end if;
end process P_TTL_HIGH_CONV;
signal s_ttl_high_sfx : sfixed(13 downto -2);
Why is s_ttl_high defined as unsigned, when s_ttl_high_sfx is signed?
Your code is not illegal, and kind of should work. But any -ve values are actually a very large unsigned value, but I guess this is how it is supposed to work (if the signed is all 1s, then you need to count a long time before turning off s_tx_p/n).
Just to be sure, try this instead (as it will pass in simulation):
s_ttl_high <= unsigned( to_signed(s_ttl_high_sfx(s_ttl_high_sfx'left downto 0)));
Have you looked at the post synthesis viewer? Tracing the outputs back and seeing what the synthesis did might shed some light on the problem.
-- P_WDW_SPL: The window si sampled to match pulse length. A new window value
-- is applied on each chirp ZC
P_WDW_SPL: process(i_clk)
begin
if (i_clk'event and i_clk = '1') then
if (s_tx_cr_zc = '1') then
s_wdw_spl <= s_hmg(to_integer(s_tx_tmr));
end if;
end if;
end process P_WDW_SPL;
signal s_hmg : mem_type_hamming:= init_mem_hamming("Hamming_10ms.mif");
Here is your problem.
Quartus does not support the initialisation of Constants in VHDL via textio. Xilinx ISE does. It's an issue I raised with Altera a long long time ago, and still isnt supported.
So your rom is initialised to all 0.
You need to do one of the following:
1. Use an attribute to point to the .mif file
2. Use an actual defined constant.
3. Use an initialisation function that computes values directly in VHDL.
- - - Updated - - -
PS. If s_hmg is a ROM, why is it declared as a signal?
signal s_hmg: mem_type_hamming;
attribute ram_init_file : string;
attribute ram_init_file of s_hmg: signal is "Hamming_10ms.mif";
"Warning (10541): VHDL Signal Declaration warning at tx_and_replica.vhd(135): used implicit default value for signal "s_hmg" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations."
And the memory is optimized away again.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 function init_rom return mem_type_hamming is variable tmp : mem_type_hamming := (others => (others => '0')); begin for addr_pos in 0 to 1023 loop -- Initialize each address with the address itself tmp(addr_pos) := to_unsigned(addr_pos, 16); end loop; return tmp; end init_rom; signal s_hmg: mem_type_hamming := init_rom;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TYPE mem_type_hamming IS ARRAY (0 TO 1023) OF UNSIGNED(15 DOWNTO 0); function hamming_init return mem_type_hamming is variable tmp : mem_type_hamming := (others => (others => '0')); constant a : real := 0.53836; constant b : real := 1.0 - a; constant scale : real := 2.0**16-1.0; variable hann: real; begin for addr_pos in 0 to 1023 loop hann := a - b*cos(MATH_2_PI*real(addr_pos)/1023.0); tmp(addr_pos) := to_unsigned(integer(scale*hann),16); end loop; return tmp; end hamming_init;
I don't know why the board designer has decided to give only JTAG access to the serial EPCS4, and not to the FPGA.
I presume you mean serial programmer connection. JTAG programming of serial flash (EPCSxx) goes through the FPGA and allows debugging as well.
I presume you mean serial programmer connection. JTAG programming of serial flash (EPCSxx) goes through the FPGA and allows debugging as well.
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