VHDL testbench problem

[calvinngu]

Hi,

Can anyone tell me how to write testbench for clock with offset.
Here is my test bench

process
begin
clk1 <= '1'; wait for 10ns;
clk1 <= '0';wait for 10ns;
end process;

process
begin
clk2 <= '0';(other signal);wait for 5ns;
clk2 <= '1';(others signal);wait for 10ns;
clk2 <= '0';(others signal);wait for 10ns;
...until 100 000 loop.
end process;

can anyone got way to write clk2 as too tire to write every change of clk2 and this way make the code so long.

Hope to see everyone reply soon.

Thanks.