int19
Newbie level 6
I hope someone can help me.
I wrote a VHDL testbench but after the place&route process the netlist is a Verilog one. So, when I try to compile the project NCSim find errors like this:
ncelab: *E,CFMPMC (../topPAD.v,1149131|14): Port direction (Verilog) and mode (VHDL) are not compatible - inout/in.
inout clk200;
All the ports that in the Verilog netlist appear as INOUT type were of IN type in the RTL level VHDL.
Anyone knows some solution?
I wrote a VHDL testbench but after the place&route process the netlist is a Verilog one. So, when I try to compile the project NCSim find errors like this:
ncelab: *E,CFMPMC (../topPAD.v,1149131|14): Port direction (Verilog) and mode (VHDL) are not compatible - inout/in.
inout clk200;
All the ports that in the Verilog netlist appear as INOUT type were of IN type in the RTL level VHDL.
Anyone knows some solution?