VHDL testbench of a Verilog netlist

[int19]

I hope someone can help me.
I wrote a VHDL testbench but after the place&route process the netlist is a Verilog one. So, when I try to compile the project NCSim find errors like this:

ncelab: *E,CFMPMC (../topPAD.v,1149131|14): Port direction (Verilog) and mode (VHDL) are not compatible - inout/in.
inout clk200;

All the ports that in the Verilog netlist appear as INOUT type were of IN type in the RTL level VHDL.
Anyone knows some solution?

 

[aji_vlsi]

My guess is you have a component declaration in VHDL that uses IN mode. But why are all ports INOUT in netlist? You should fix that first.

Show us the Verilog module port list, VHDL component declaration for more help

Ajeetha, CVC
www.noveldv.com

 

[int19]

Thanks for your answer. I'm very sorry but I made some mistake.
Effectively the ports I thought to be IN were INOUT, I had an old version of vhdl.
Thanks again.