VHDL + SV in UVM in VCS

[nyamars]

Can anyone please tell me how to compile VHDL (DUT files) and SV files in UVM environment in VCS?

 

[meir]

3 stages, see vcsmx_ug.pdf for more details
compile:
vhdlan <vhdl design files>
vlogan <verilog design files>
vlogan -ntb_opts uvm (no source files)
vlogan -ntb_opts uvm <sv uvm files>
elaborate:
vcs <top_module>
run:
./simv