Of course as I dislike all the type conversions, you'll have to work that out yourself, along with the loop that will be needed to iterate over the duration you desire.
In Verilog I would have done something like this:
Code:
initial begin
x = 0;
# some_offset_delay;
forever begin
x = #10 x + 1;
end
end
Sounds like a "My first testbench - part 2" problem, because every testbench for sequential logic involves clock generation, and incrementing an integer or real signal together with clock generation would be the next step.