VHDL simulation with type "time"

[shaiko]

Hello,

x is defined as:

signal x: std_logic_vector ( 7 downto 0 ) ;

I want 'x' to be incremented by 1 with relation to the simulation time - for example:

"00000000" at time: 10 ns
"00000001" at time: 20 ns
"00000010" at time: 30 ns

The obvious will be:

x <= 
"00000000" after 10 ns , 
"00000001" after 20 ns ,
"00000010" after 30 ns ;

But because the time interval is constant ( 10 ns ) I'm looking for a way to do the same in an iterative form.
Please post an example.

 

[ads-ee]

why not just do the obvious?

x <= x + 1 after 10 ns;

Of course as I dislike all the type conversions, you'll have to work that out yourself, along with the loop that will be needed to iterate over the duration you desire.

In Verilog I would have done something like this:

initial begin
  x = 0;
  # some_offset_delay;
  forever begin
    x = #10 x + 1;
  end
end

 

[FvM]

Sounds like a "My first testbench - part 2" problem, because every testbench for sequential logic involves clock generation, and incrementing an integer or real signal together with clock generation would be the next step.

 

[shaiko]

ads-ee,

Can you write conditional statements using type "time"
For example:

if time = 500 ns then
...

If it's possible - please post an example.

 

[K-J]

ads-ee,

Can you write conditional statements using type "time"
For example:

if time = 500 ns then
...

If it's possible - please post an example.

if now = 500 ns then

Kevin Jennings