Nov 30, 2014 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Hello, Signal x is a simulated clock that's defined as follows: Code: signal x : std_logic := '0' ; x <= not x after 10ns ; Suppose, I want x to start running after 100ns and stop after 1000ns. The obvious solution will be to mux it...my question: Is there a simple simulation syntax that allows to do that without using a mux?
Hello, Signal x is a simulated clock that's defined as follows: Code: signal x : std_logic := '0' ; x <= not x after 10ns ; Suppose, I want x to start running after 100ns and stop after 1000ns. The obvious solution will be to mux it...my question: Is there a simple simulation syntax that allows to do that without using a mux?
Nov 30, 2014 #2 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 You can use this. x <= '0', not x after 100 ns, '0' after 1000 ns;
Nov 30, 2014 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 sharath666 said: You can use this. x <= '0', not x after 100 ns, '0' after 1000 ns; Click to expand... That wont make a clock, that will just set it high for 900 ns. The easiest option is a mud like you suggested, or a process with control loops.
sharath666 said: You can use this. x <= '0', not x after 100 ns, '0' after 1000 ns; Click to expand... That wont make a clock, that will just set it high for 900 ns. The easiest option is a mud like you suggested, or a process with control loops.
Nov 30, 2014 #4 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 a process with control loops. Click to expand... Can you post an example please ?
Nov 30, 2014 #5 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 Process Begin input <= '0'; wait for 100ns; for I in 1 to 90 loop input <= not input; wait for 10 ns; end loop; input <= '0'; End process;
Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 Process Begin input <= '0'; wait for 100ns; for I in 1 to 90 loop input <= not input; wait for 10 ns; end loop; input <= '0'; End process;
Nov 30, 2014 #6 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,501 Helped 14,757 Reputation 29,796 Reaction score 14,124 Trophy points 1,393 Location Bochum, Germany Activity points 298,445 A terminating wait statement should stop further process schedule.