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VHDL - Signal xx cannot be synthesized, bad synchronous desc

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tarek-

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bad synchronous description

I have written a 4-bit ALU with CCR in VHDL, but when I try to obtain the Synthesis Report in Xilinx ISE 9.2i I get this error:

line 39: Signal C cannot be synthesized, bad synchronous description.

Line 39 is: " PROCESS(s, CLK) IS"

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU4bit is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (3 downto 0);
			  CLK : in STD_LOGIC;
           V, N, Z, C : out  STD_LOGIC;           
           f : out  STD_LOGIC_VECTOR (3 downto 0));
--			  SEV_SEG: out STD_LOGIC_VECTOR (7 downto 1));
end ALU4bit;

architecture Behavioral of ALU4bit is

begin

	PROCESS(s, CLK) IS
		VARIABLE temp, carry: STD_LOGIC_VECTOR(4 DOWNTO 0); -- extra bit is for Cout in arithmetic operations
		VARIABLE A: STD_LOGIC_VECTOR(3 DOWNTO 0) := x;
		VARIABLE B: STD_LOGIC_VECTOR(3 DOWNTO 0) := y;
		VARIABLE k, sub: STD_LOGIC := '0';	
	BEGIN
	  	
	-- initialize variables and outputs
		C <= '0';
		V <= '0';
		N <= '0';
		Z <= '0';	
		sub := '0';
		carry(4 downto 0) := "XXXXX";
		
   IF (CLK = '1' AND CLK'event) THEN
		
		CASE s IS

	-- arithmetic operations: s(3) = 0	
	
			WHEN "0000" =>
				temp := ('0' & A); -- transfer x to temp
			WHEN "0001" =>
				temp := ('0' & A)+1; -- increment x by 1
			WHEN "0010" =>
				temp := ('0' & A)+B; -- add y to x
			WHEN "0011" =>
				temp := ('0' & A)+B+1; -- add y and Cin to x
			WHEN "0100" => 
				B := NOT B;
				temp := ('0' & A)+ B; -- subtract y from x (one's complement subtraction)
				sub := '1';
			WHEN "0101" =>
			   B := NOT B;
				temp := ('0' & A)+ B +1; -- subtract y from x and increment (two's complement subtraction)
				sub := '1';
			WHEN "0110" =>
				temp := ('0' & A) - 1; -- decrement x
				sub := '1';
			WHEN "0111" =>
				temp := ('0' & B); -- transfer y to temp

	-- logical operations: s(3) = 1

			WHEN "1000" =>
				temp := NOT ('0' & B); -- invert y
			WHEN "1001" =>
				temp := ('0' & (A NAND B)); -- logical nand of x and y
			WHEN "1010" =>
				temp := ('0' & (A NOR B)); -- logical nor of x and y
			WHEN "1011" =>
				temp := ('0' & (A XNOR B)); -- logical xnor of x and y
			WHEN "1100" =>
				temp := ('0' & (A XOR B)); -- logical xor of x and y
			WHEN "1101" =>
				temp := ('0' & (A OR B)); -- logical or of x and y
			WHEN "1110" =>
				temp := ('0' & (A AND B)); -- logical and of x and y
			WHEN OTHERS =>
				temp := NOT ('0' & A); -- invert x
		END CASE;

	-- output assignment
	
		IF s(3) = '0' THEN -- only consider CCR in arithmetic mode
		
		-- determine negative bit, N
			IF temp(3) = '1' THEN
				N <= '1';
			END IF;			
	
		-- determine overflow bit, V
			carry(0) := '0';
			for k in 1 to 4 loop
				carry(k) := (A(k-1) AND B(k-1)) OR (carry(k-1) AND (A(k-1) XOR B(k-1)));
			end loop;
			
			IF (carry(4) XOR carry (3)) = '1' THEN
				V <= '1';
			END IF;
			
      -- determine zero bit, Z
			IF temp(3 downto 0) = "0000" THEN
				Z <= '1';
			END IF;
			
		-- determine carry bit, C
			IF ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) THEN
				C <= '1';
			END IF;		

		END IF;
		
		-- determine output, f

		f <= temp(3 downto 0);	
	
   ELSE -- When CLK is low, give garbage output
		f <= "XXXX";
		C <= 'X';
		V <= 'X';
		N <= 'X';
		Z <= 'X';
	END IF;
	
	END PROCESS;
END Behavioral;


The code passes the syntax check and the testbench provides the correct waveforms. The Xilinx documentation on this error does help. I tried replacing the nested IF statements with the bottom block of code to determine the state of the CCR but I get more errors.

Code: 
carry(0) := '0';
for k in 1 to 4 loop
	carry(k) := (A(k-1) AND B(k-1)) OR (carry(k-1) AND (A(k-1) XOR B(k-1)));
end loop;
V <= '1' WHEN (carry(4) XOR carry (3)) = '1' ELSE '0';
N <= '1' WHEN temp(3) = '1' ELSE '0';			
Z <= '1' WHEN temp(3 downto 0) = "0000" ELSE '0';
C <= '1' WHEN ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) ELSE '0';

Any suggestions are appreciated.

edit: I found that removing the clock fixes the error, but i need this program to have a clock. The xilinx doc mentioned something about 'EVENT and IF statements but I didn't understand.

**broken link removed**
 

bad synchronous description vhdl

Hi,
I think 'else' part for if (clk'event and clk = '1') is causing a problem, else to 'event is not synthesizable. Modify the code accordingly.
 

how to invert a signal under vhdl

PROCESS(s, CLK) IS

This is a synchronous discription of an ALU. What do you have if you use:

PROCESS(CLK) IS

Added after 15 seconds:

PROCESS(s, CLK) IS

This is an asynchronous discription of an ALU. What do you have if you use:

PROCESS(CLK) IS
 

vhdl loop nested if then else

I still get the problem when I remove the ELSE statement. If I change to process(CLK) the error is still there...

very strange. I moved the code under the ELSE to the top where the input/output initialization is and doesnt work, but when I comment out this code i can synthesize. any idea why?

Code: 
f <= "XXXX";
C <= 'X';
V <= 'X';
N <= 'X';
Z <= 'X';
 

signal cannot be synthesized

You are setting C, (and your other signals) to 1 if a copndition occurs, but you are not resseting them.

In every if statement, include and else statement to set the bit to 0 if the condition is not met.

That may fix your problem (and should be done anyway).
 

xilinx error bad synchronous description

What tool are U using for synthesis ?
 

4 bit addition alu vhdl

The signals are all initialized to 0 after BEGIN in process statement. that is not enough? should the ELSE statement be in the 'output assignment' section then? i am using xilinx ise 9.2i, installing quartus 7.2 right now also.

Code: 
		IF s(3) = '0' THEN -- only consider CCR in arithmetic mode
		
		-- determine negative bit, N
			IF temp(3) = '1' THEN
				N <= '1';
			ELSE
			   N <= '0';
			END IF;			
	
		-- determine overflow bit, V
			-- calculate carry at each step in the arithmetic operation
			carry(0) := '0';
			for k in 1 to 4 loop
				carry(k) := (A(k-1) AND B(k-1)) OR (carry(k-1) AND (A(k-1) XOR B(k-1)));
			end loop;
			
			IF (carry(4) XOR carry (3)) = '1' THEN
				V <= '1';
			ELSE
			   V <= '0';
			END IF;
			
      -- determine zero bit, Z
			IF temp(3 downto 0) = "0000" THEN
				Z <= '1';
			ELSE
			   Z <= '0';				
			END IF;
			
		-- determine carry bit, C
			IF ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) THEN
				C <= '1';
			ELSE
			   C <= '0';
			END IF;		

		END IF;

still doesnt work...
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

No you need to reset them to zero, if you don't have that in your code, your carry will remain as 1 after it is set for the first time. I assume you don't want that.

Without playing around with the code myself it is hard to say what the exact error is. Although, seeing as it is a 'bad synchronous description', error then it narrows it down to the if statement describing C.

IF ((sub = '1' AND y > x) OR (sub = '0' AND temp(4) = '1')) THEN

I guess that there are conditions in there which can't be resolved exactly.

try changing it to
IF ((j) OR (k)) THEN

with j and k being processed synchounously elsewhere, with an
IF (CLK = '1' AND CLK'event) THEN
IF ((sub = '1' AND y > x)
j:=1;
else
j:=0;
etc

or similar.

that will at least help you narrow down which signal is causing the error.
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

that part of the code i don't think is causing problems. its when i address the state where clk is low, i want all outputs as X. i put the ELSE and i get 'bad synchronous description'. i take else out and initialize all outputs as X before the IF (clk=1 and clk'event) and still get 'bad synchronous description'. i dont know what is causing this.
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

if you do what I suggest above, you'll find out what's causing it, or you'll know which of those two expressions is giving you the problem (if either, but I'd lay good money on it being in there!). It's up to yourself though.
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

I have followed your suggestion and still get the error.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU4bit is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (3 downto 0);
			  CLK : in STD_LOGIC;
           V, N, Z, C : out STD_LOGIC := '0';           
           f : out  STD_LOGIC_VECTOR (3 downto 0));
--			  SEV_SEG: out STD_LOGIC_VECTOR (7 downto 1));
end ALU4bit;

architecture Behavioral of ALU4bit is

begin

	PROCESS(s, CLK) IS 
		VARIABLE temp, carry: STD_LOGIC_VECTOR(4 DOWNTO 0); -- temp stores result of operation and carry out. carry is individual carry bits
		VARIABLE A: STD_LOGIC_VECTOR(3 DOWNTO 0); -- allows input x to be modified
		VARIABLE B: STD_LOGIC_VECTOR(3 DOWNTO 0); -- allows input y to be modified
		VARIABLE k, sub: STD_LOGIC; -- counter and indication of subtraction operation respectively
		VARIABLE t1, t2: BOOLEAN ;
	BEGIN
	  	
	-- initialize variables and outputs
		f <= "0000";
		C <= '0';
		V <= '0';
		N <= '0';
		Z <= '0';
		sub := '0';
		A := x;
		B := y;
		carry(4 downto 0) := "00000"; -- stores carry bits, necessary for determining overflow
		
   IF (CLK = '1' AND CLK'event) THEN
		
		CASE s IS

	-- arithmetic operations: s(3) = 0	
	
			WHEN "0000" =>
				temp := ('0' & A); -- transfer x to temp
			WHEN "0001" =>
				temp := ('0' & A)+1; -- increment x by 1
			WHEN "0010" =>
				temp := ('0' & A)+B; -- add y to x
			WHEN "0011" =>
				temp := ('0' & A)+B+1; -- add y and Cin to x
			WHEN "0100" => 
				B := NOT B;
				temp := ('0' & A)+ B; -- subtract y from x (one's complement subtraction)
				sub := '1';
			WHEN "0101" =>
			   B := NOT B;
				temp := ('0' & A)+ B +1; -- subtract y from x and increment (two's complement subtraction)
				sub := '1';
			WHEN "0110" =>
				temp := ('0' & A) - 1; -- decrement x
				sub := '1';
			WHEN "0111" =>
				temp := ('0' & B); -- transfer y to temp

	-- logical operations: s(3) = 1

			WHEN "1000" =>
				temp := NOT ('0' & B); -- invert y
			WHEN "1001" =>
				temp := ('0' & (A NAND B)); -- logical nand of x and y
			WHEN "1010" =>
				temp := ('0' & (A NOR B)); -- logical nor of x and y
			WHEN "1011" =>
				temp := ('0' & (A XNOR B)); -- logical xnor of x and y
			WHEN "1100" =>
				temp := ('0' & (A XOR B)); -- logical xor of x and y
			WHEN "1101" =>
				temp := ('0' & (A OR B)); -- logical or of x and y
			WHEN "1110" =>
				temp := ('0' & (A AND B)); -- logical and of x and y
			WHEN OTHERS =>
				temp := NOT ('0' & A); -- invert x
		END CASE;

	-- output assignment
	
		IF s(3) = '0' THEN -- only consider CCR in arithmetic mode
		
		-- determine negative bit, N
			IF temp(3) = '1' THEN
				N <= '1';
			END IF;			
	
		-- determine overflow bit, V
			-- calculate carry at each step in the arithmetic operation
			carry(0) := '0';
			for k in 1 to 4 loop
				carry(k) := (A(k-1) AND B(k-1)) OR (carry(k-1) AND (A(k-1) XOR B(k-1)));
			end loop;
			
			IF (carry(4) XOR carry (3)) = '1' THEN
				V <= '1';
			END IF;
			
      -- determine zero bit, Z
			IF temp(3 downto 0) = "0000" THEN
				Z <= '1';
			END IF;
			
		-- determine carry bit, C
			IF (sub = '1' AND y > x) THEN
				t1 := TRUE;
			ELSE
				t1 := FALSE;
			END IF;
			IF (sub = '0' AND temp(4) = '1') THEN
				t2 := TRUE;
			ELSE
				t2 := FALSE;
			END IF;		
		
			IF (t1 OR t2) THEN
				C <= '1';
			END IF;
			
		ELSE
			C <= '0';
			Z <= '0';
			N <= '0';
			V <= '0';
		END IF;
		
		-- determine output, f

		f <= temp(3 downto 0);	
		
	ELSE
		f <= "XXXX";
		C <= 'X';
		V <= 'X';
		N <= 'X';
		Z <= 'X';	
	END IF;
	
	END PROCESS;
END Behavioral;

Added after 10 minutes:

the problem is not just with C, its with all the outputs. when i comment out all references to C, it complains abuot N, and so on for the rest of them when i comment out one by one. the only solution is to take out the ELSE but i need that part of the code.
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

put each one in their ownprocess with if (clk'event and clk=1), and pass them to the current one is what I meant you to do. I assume that is legel, it has been a couple of years since I programmed VHDL, but I don't think there should be a problem doing that.

then the error will point to the one with the synchronous problem, thus narrowing down where the actual error is. As it is I imagine it is still pointing to the same line as it did initially.

It is certainly an error with the clock, and with the setting of C, thus it has to be somewhere in that statement. You are going to have to find a way of rewriting it, but you first need to know which part to focus your attention on. There may be a beter way of finding the error, but I can't think of one.

Added after 2 minutes:

try making them signals instead of variables then.

I just noticed that else statement, the problem there is that it is not going to give garbage (although it may), it is going to give you a 1 or a 0, probably the last value, and it cannot write a X, thus it cannot be synthesized.
 

Well in the testbench it does give X for low CLK. I think the underlying problem is that although the code is syntactially correct and works in simulator, there is no such resource )or set of resources) which matches the behavior modeled in the code thus it can't be synthesized. I'm doing some restructuring and reorganizing now, hopefully it will work...
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

tarek- said:
Well in the testbench it does give X for low CLK. I think the underlying problem is that although the code is syntactially correct and works in simulator, there is no such resource )or set of resources) which matches the behavior modeled in the code thus it can't be synthesized. I'm doing some restructuring and reorganizing now, hopefully it will work...
Click to expand...

the test bench will give an x, but there is no such thing in the real world. You can not care about an output value, but something has to be hardwired to it. the synthesizer has to know what you want it to do.
 

replaced X with 0, no luck...
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

That statement is effectively trying to write on both edges of the clock which is also not possible in VHDL.
You're going to have to restructure your code somewhat.
 

Re: VHDL - Signal xx cannot be synthesized, bad synchronous

Signals that change on a clock event are modelled with registers. The registers on a Xilinx FPGA remain stable until there is a clock event, or a higher priority set or reset condition. An undefined state is an invalid state - it cannot be synthesized. Your process must reflect this reality.

Negation of a clock event is "nonevent". In the ELSE of a clock event, you are basically asking the circuit to maintain a specified output state when the clock signal is stable - and a clock signal is stable between clock edges (events). This completely negates any attempt at changing the output state.
 

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