derrick_chi
Junior Member level 3
I need to know what exactly is wrong with the design of this STATE MACHINE. I need someone to take a look and help me out with this one.
entity Test1_Module is
PORT (clk_count: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);
finished1, RST, CLK, INPUT_SIGNAL1, INPUT_DELAYED : IN STD_LOGIC;
ld_output, up_down, done, ld_accs, clr_count, cnt_cntrl, SEL1: OUT STD_LOGIC;
max_sc : OUT INTEGER RANGE 0 TO 256 );
end Test1_Module;
architecture Behavioral of Test1_Module is
TYPE state IS (state0, state1, state2, state3, state4);
SIGNAL pr_state, nx_state : state;
begin
process (clk,rst)
begin
if (rst ='1') then
pr_state <= state0;
elsif (clk'Event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
process (pr_state, clk_count, finished1)
begin
case pr_state is
when state0 =>
nx_state <= state1;
when state1 =>
if ( clk_count = 5 ) then
nx_state <= state2;
else
nx_state <= state1;
end if;
when state2 =>
if ( finished1 = '1' ) then
nx_state <= state3;
else
nx_state <= state2;
end if;
when state3 =>
if ( finished1 = '1' ) then
nx_state <= state4;
else
nx_state <= state3;
end if;
when state4 =>
nx_state <= state4;
end case;
end process;
process (pr_state)
begin
case pr_state is
when state0 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
SEL1 <= '0';
max_sc <= 0;
when state1 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
SEL1 <= '0';
max_sc <= 0;
cnt_cntrl <= '1';
if ( input_signal1 = '1' and input_delayed = '1') then
ld_accs <= '1';
clr_count <= '1';
else
ld_accs <= '0';
clr_count <= '0';
end if;
when state2 =>
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
max_sc <= 0;
done <= '0';
SEL1 <= '0';
if ( finished1 = '1' ) then
ld_output <= '1';
else
ld_output <= '0';
end if;
when state3 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
SEL1 <= '1';
max_sc <= 255;
when state4 =>
ld_output <= '0';
SEL1 <= '1';
up_down <= '0';
done <= '1';
ld_accs <= '0';
cnt_cntrl <= '1';
clr_count <= '0';
max_sc <= 255;
end case;
end process;
end Behavioral;
entity Test1_Module is
PORT (clk_count: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);
finished1, RST, CLK, INPUT_SIGNAL1, INPUT_DELAYED : IN STD_LOGIC;
ld_output, up_down, done, ld_accs, clr_count, cnt_cntrl, SEL1: OUT STD_LOGIC;
max_sc : OUT INTEGER RANGE 0 TO 256 );
end Test1_Module;
architecture Behavioral of Test1_Module is
TYPE state IS (state0, state1, state2, state3, state4);
SIGNAL pr_state, nx_state : state;
begin
process (clk,rst)
begin
if (rst ='1') then
pr_state <= state0;
elsif (clk'Event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
process (pr_state, clk_count, finished1)
begin
case pr_state is
when state0 =>
nx_state <= state1;
when state1 =>
if ( clk_count = 5 ) then
nx_state <= state2;
else
nx_state <= state1;
end if;
when state2 =>
if ( finished1 = '1' ) then
nx_state <= state3;
else
nx_state <= state2;
end if;
when state3 =>
if ( finished1 = '1' ) then
nx_state <= state4;
else
nx_state <= state3;
end if;
when state4 =>
nx_state <= state4;
end case;
end process;
process (pr_state)
begin
case pr_state is
when state0 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
SEL1 <= '0';
max_sc <= 0;
when state1 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
SEL1 <= '0';
max_sc <= 0;
cnt_cntrl <= '1';
if ( input_signal1 = '1' and input_delayed = '1') then
ld_accs <= '1';
clr_count <= '1';
else
ld_accs <= '0';
clr_count <= '0';
end if;
when state2 =>
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
max_sc <= 0;
done <= '0';
SEL1 <= '0';
if ( finished1 = '1' ) then
ld_output <= '1';
else
ld_output <= '0';
end if;
when state3 =>
ld_output <= '0';
up_down <= '1';
done <= '0';
ld_accs <= '0';
clr_count <= '1';
cnt_cntrl <= '0';
SEL1 <= '1';
max_sc <= 255;
when state4 =>
ld_output <= '0';
SEL1 <= '1';
up_down <= '0';
done <= '1';
ld_accs <= '0';
cnt_cntrl <= '1';
clr_count <= '0';
max_sc <= 255;
end case;
end process;
end Behavioral;