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vhdl or verilog !!!!!

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prashanthi999

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i have done 1 year internship in vhdl and good with it, but my faculty says verilog will dominate the world lately, is it k to be with just vhdl or I should learn verilog keeping future in view!!!???
 

dick_freebird

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VHDL persists in (US domestic) military and government uses,
and academia, but commercial has pretty much gone to verilog
(and veriloga, is much better supported in mixed signal simulators
than any sort of vhdl based equivalent, if indeed any exist).

I'd say to keep what you learn about style, and plan on picking
up the veriloga syntax & tools for the future. Because the tool
set you will use (for any but the independent designer) is the
employer's choice, not yours, and employers tend to choose
the leading tool vendors' packages (commercial, supported)
and therefore a job in industry will put you on that horse.
 

artmalik

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well it is sort of true that Verilog is preferred languages in many companies..... it has gained importance over the past year... it is better to move to Verilog ....
 

ads-ee

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Now you've done it...poke a stick in the hornet's nest. 8-O ;-)

Neither language is going to disappear in the foreseeable future. The only reason Verilog is more visible now is due to the adoption of System Verilog for testbenches due to UVM. And we all know UVM is the big buzz word in verification now.

Personally knowing both languages is a good thing. Just like software engineers typically have expertise in 3 or more languages, those that have only expertise in one (e.g. Cobol) are on the road to a dead end career.
 

SynthWorks

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It is actually quite simple. Make a short list of companies you want to work for. Find out what they use. Learn that.

What is the market really doing? Currently a basic SystemVerilog simulator costs much more than a VHDL simulator. EDA vendors have made a big push to get people to switch. Hence, they have taught everyone the mantra "SystemVerilog/UVM for verification". However, this is not statistics.

Based on the 2012 Wilson Survey (sponsored by Mentor),
ASIC Design: 33% VHDL 75% Verilog
FPGA Design: 73% VHDL 53% Verilog
FPGA Verification: 62% VHDL 42% Verilog 29% SystemVerilog
More details are here:
http://blogs.mentor.com/verificatio...research-group-functional-verification-study/

Let me teach you another mantra: OSVVM for VHDL Verification.
OSVVM is a free, open source set of packages that allow you to use a basic VHDL simulator to do functional coverage, constrained random (so-so), and Intelligent Coverage randomization (better than constrained random and not available in SystemVerilog/UVM).

More on OSVVM is available at: http://www.synthworks.com/blog/osvvm/ and http://osvvm.org/

Disclaimer: I am the chief architect of OSVVM and a VHDL advocate.
 
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