ENTITY wr_text IS
GENERIC(
out_width : positive := 16
);
PORT(
clk : IN std_logic;
en_i : IN std_logic;
datai : IN unsigned (out_width-1 DOWNTO 0)
);
-- Declarations
END wr_text ;
--
ARCHITECTURE files OF wr_text IS
signal en_o : std_logic;
BEGIN
write_txt: process(clk)
variable outline :line;
file outputfile : text open append_mode is "sqrr_output.txt";
begin
if (rising_edge(clk)) then
if (en_i = '1') then
write(outline,datai); -- line 41
writeline(outputfile,outline);
en_o <= '1';
end if;
end if;
end process;-- line 49