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[SOLVED] vhdl : No feasible entries for subprogram "write".

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rakeshk.r

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HI, I am using HDL designer, I created a component "wr_text" by adding an existing .vhd file to my current design project. The code is pretty straight forward, I wanted to write out the unsigned input data to a text file. The code is shown below:
Code:
ENTITY wr_text IS
   GENERIC( 
      out_width : positive := 16
   );
   PORT( 
      clk   : IN     std_logic;
      en_i  : IN     std_logic;
      datai : IN     unsigned (out_width-1 DOWNTO 0)
   );

-- Declarations

END wr_text ;

--
ARCHITECTURE files OF wr_text IS
signal en_o : std_logic;  
BEGIN
write_txt: process(clk)
variable outline :line;
file outputfile : text open append_mode is "sqrr_output.txt";
begin
if (rising_edge(clk)) then 
  
  if (en_i = '1') then 
        
        write(outline,datai); -- line 41
        writeline(outputfile,outline);
        en_o <= '1';
            
    end if;
    
end if; 
end process;-- line 49

I am getting an compilation error as shown below:
HTML:
Performing compile...
Library lns_project_lib
Writing temporary output file "/tmp/Files0".
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity wr_text
-- Compiling architecture files of wr_text
** Error: /site/path1/path2/path3/user/folder1/lns/lns_project/lns_project_lib/hdl/wr_text_files.vhd(41): No feasible entries for subprogram "write".
** Error: /site/path1/path2/path3/user/folder1/lns/lns_project/lns_project_lib/hdl/wr_text_files.vhd(49): VHDL Compiler exiting

child process exited abnormally
Failed during ModelSim compile  - Error executing  "/sw/mentor/modelsim_10.0/modeltech/bin/vcom -work "lns_project_lib" -nologo -f /tmp/Files0"

Compiled 1 file(s) in 1 compiler invocation(s) with 2 failure(s)

However when I created a new interface "wr_bin" rather than adding an existing vhdl file, I put the same code as shown above in "wr_bin" and compiled it. Strange! (but fortunate) that it compiled succesfully.
HTML:
Performing compile...
Library lns_project_lib
Writing temporary output file "/tmp/Files0".
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity wr_bin
-- Compiling architecture data of wr_bin

Compiled 1 file(s) in 1 compiler invocation(s) with 0 failure(s)
Compilation took 0 second(s)
Data preparation step completed, check transcript...
---------------------------------------------------------------------------------
Simulation directory is set to /site/path1/path2/path3/user/folder1/lns/lns_project/lns_project_lib/work
Saving Symbol for Design Unit lns_project_lib/wr_text

One difference can be found by looking at the figures of these component attached with this query. The input port "datai" declaration in "wr_text" doesn't show up similar to "wr_bin" component. I don't know the reason behind this difference. But, still I am not sure why I have that compilation error for the component "wr_text". For now I have a working component but still I am curious to know the fix to this error. Your comments towards solving this error is appreciated.
 

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ads-ee

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You didn't include the textio package in your code with a
Code:
library std;
use std.textio.all;
 

rakeshk.r

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You didn't include the textio package in your code with a
Code:
library std;
use std.textio.all;

This is how I have declared the packages in that file:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;

So I have used std.textio package. Also you can see the compiler transcript showing
Loading package TEXTIO
.
 

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Sorry didn't realize you had the results of the compile posted....you didn't include the library declarations in your code. You shouldn't leave out those when posting VHDL code, because it always matters, which libraries you load.

From the textio package:
Code:
  procedure WRITE (L: inout LINE; VALUE: in BIT;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in BOOLEAN;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in CHARACTER;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in INTEGER;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in REAL;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;
			DIGITS: in NATURAL := 0);

  procedure WRITE (L: inout LINE; VALUE: in STRING;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);

  procedure WRITE (L: inout LINE; VALUE: in TIME;
			JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;
			UNIT: in TIME := ns);
There is no definition for a write done using the data type unsigned. convert it to an integer.
 

TrickyDicky

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There is no write function for numeric std. You have a few options:

1. Include the non-standard std_logic_textio package and convert your unsigned to a std_logic_vector before using the write, owrite or hwrite functions
2. Convert the unsigned to an integer or bit_vector
3. Use VHDL 2008. Each package has textio functions built in so you can write/owrite/hwrite any vector type (and theres other stuff like to_string/to_ostring/to_hstring too)
 

rakeshk.r

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AHH! Now I see why the vhdl file ("wr_text") which I added from a existing project didn't work for me. It is not the 2008 version in the current design unit. But this original vhdl file was created in 2008 version and I remember it working well with a signed input data. I am wondering how by just importing a 2008 version vhdl file into a new project, can turn it into a non-2008 version. Any ways thanks for the insight.
 

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