Veriliog code itself has been tested and post simulation results have been passed. I added several blocks and it gives same message to all modules without exception....
Modules are connected through the amba AHB bus ...
In your system is it possible to remove some blocks and try to do the synthesis. What I mean is, is it possible to locate the module which is giving error by isolating it in the synthesis.
Also check for any prior warnings.There may be hint in those warnings.
1.) you forgot something on the line above this one, and the error is reported on this line.
2.) you didn't declare "my_istance". eg, there should be a package or a component delaration somewhere. If this is autogen, it might not have included this.
and its likely the latter. After all, if my_inst isn't defined, the line could be multiple things. That would make a more discriptive error difficult for the parser to report.