titanic
Newbie level 6
VHDL netlist.
Hi,
In libero, I wrote a verilog code and generated VHDL netlist of the code and connected VHDL netlist to another VHDL project.
However, synplify gives the following error message after long compilation .
@E: CD708 :"C:\AAAAA\XXXXX.vhd":82:22:82:35|Not a concurrent statement.
does anybody have an idea..?
Hi,
In libero, I wrote a verilog code and generated VHDL netlist of the code and connected VHDL netlist to another VHDL project.
However, synplify gives the following error message after long compilation .
@E: CD708 :"C:\AAAAA\XXXXX.vhd":82:22:82:35|Not a concurrent statement.
does anybody have an idea..?