VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

[titanic]

VHDL netlist.

Hi,

In libero, I wrote a verilog code and generated VHDL netlist of the code and connected VHDL netlist to another VHDL project.

However, synplify gives the following error message after long compilation .

@E: CD708 :"C:\AAAAA\XXXXX.vhd":82:22:82:35|Not a concurrent statement.

does anybody have an idea..?

 

[TrickyDicky]

VHDL netlist.

not without seeing the code. Looks like a syntax error.

 

[vipinlal]

Re: VHDL netlist.

Does the code work in simulation?

If you cant post the code,try to give the block diagram of the project.It may help.

--vipin
https://vhdlguru.blogspot.com/

 

[titanic]

Re: VHDL netlist.

Veriliog code itself has been tested and post simulation results have been passed. I added several blocks and it gives same message to all modules without exception....



Modules are connected through the amba AHB bus ...

 

[TrickyDicky]

VHDL netlist.

just because the verilog works, doesnt mean the generated VHDL is correct.

The error sounds like a syntax error. Please post the code.

 

[vipinlal]

Re: VHDL netlist.

In your system is it possible to remove some blocks and try to do the synthesis. What I mean is, is it possible to locate the module which is giving error by isolating it in the synthesis.
Also check for any prior warnings.There may be hint in those warnings.

--vipin
https://vhdlguru.blogspot.com/

 

[titanic]

Re: VHDL netlist.

Iwill check it...

..There are no prior messages btw...

 

[devas]

Re: VHDL netlist.

Have a look in the file XXXXX.vhd at line 82 and check this line.

 

[titanic]

VHDL netlist.

That line is the instantiation of the netlist... like

Inst_0 : my_istance

 

[TrickyDicky]

VHDL netlist.

Well the compiler is correct - that is not a concurrent statement. So there is still a problem with the code.

Is that line inside a process or a function?
you need to post more code around the error line please

 

[FvM]

Re: VHDL netlist.

that is not a concurrent statement

A component instantiation is a concurrent statement.

But there are various reasons why a "VHDL netlist" (I guess, it's a *.vho file) may be not accepted as design entity.

 

[permute]

VHDL netlist.

I suspect either:

1.) you forgot something on the line above this one, and the error is reported on this line.
2.) you didn't declare "my_istance". eg, there should be a package or a component delaration somewhere. If this is autogen, it might not have included this.

and its likely the latter. After all, if my_inst isn't defined, the line could be multiple things. That would make a more discriptive error difficult for the parser to report.

 

[titanic]

Re: VHDL netlist.

Hi,

thanx for the replies... I could fix it...