VHDL - Nbit multiplier test bench

[S S Rayudu]

in my test bench im supposed not to give any test vectors for my 2 bit multiplier but test should be done for all 4 possible combinations by using for loops
can some one help me with this

 

[mrflibble]

Damn. Doctor Habibi (my usual voodoo go-to guy) just went on vacation. As soon as he's back I will post an answer to your problem. Personally I have no clue wtf you are on about, but Dr Hababi is a champ at divining the full answer based on haphazard partial clues.

 

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in my test bench im supposed not to give any test vectors for my 2 bit multiplier but test should be done for all 4 possible combinations by using for loops
can some one help me with this

assuming Verilog (as my Dr Habibi died from overusing their "powers" interpreting edaboard posts) use a for loop in a initial block that assigns the for loop index to the signal that is connected to the multiplier input. You would also have a time control statement like #10 to schedule the next time through the loop, otherwise everything will be done in 0 ns.

Seems to me a 2-bit multiplier should have 16 possible input combinations (i.e. four input values for each A/B input) and would have a 4-bit output.

- - - Updated - - -

Something like this should work.

reg [1:0] a,b;
integer i;
initial begin
  for (i=0;i<16;i=i+1) begin
    {a,b} = i;
    #10;
  end
end