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[SOLVED] VHDL if statement error

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Aya2002

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Hi friends,

I am designing a FIFO handler but I face an error message in the If statement. Part of my code is:

Code:
library ieee;
use ieee.std_logic_1164.all;
-- FIFO Handler

Entity FIFO_Handler IS
	Port(Rx_Ready	: in std_logic;
		 Data		: in std_logic_vector(7 downto 0);
		 Tx_Req		: out std_logic;
		 Rd_Req		: out std_logic;
		 FIFO_clk	: out std_logic;
		 Wr_Req		: out std_logic;
		 Tx_Data	: out std_logic_vector(7 downto 0)
		 );
End FIFO_Handler;

Architecture FIFO_Handler_atl OF FIFO_Handler IS
	Signal Rx_Req	: std_logic;
	Signal Rec		: std_logic ;
	signal Temp_Reg	: std_logic_vector(7 downto 0);
--	constant delay	: Time;
Begin
--	delay := 10 ns;
	Rx_Req		<= '1';
	Rec			<= '0';
	If (Rx_Req = '1') Then
		Wr_Req 		<= '1';
		FIFO_clk 	<= '1';
--		WAIT FOR 10 us;
		FIFO_clk 	<= '0';
		Wr_Req 		<= '0';
		Rec			<= '1';
	End if;
	
	
	
	
	end FIFO_Handler_atl;
the error message is: Error (10500): VHDL syntax error at FIFO_Handler.vhd(25) near text "If"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

I think my code is now wrong :) what is your opinion?
Thank you for your help
 

FvM

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Looks like you are using if (a sequential statement) outside a process (a sequential block). That's not possible in VHDL (neither in Verilog).
 

Aya2002

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Thank you both of you

Solved. It must be inside a process.
 

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